XC2164 Series
■SWITCHING CHARACTERISTICS
XC2164Ax1M, T, V (Fundamental) <Chip Enable>
(unless otherwise stated, VDD=3.3V or 5.0V, Ta= -30~+80℃)
PARAMETER
SYMBOL
tr
CONDITIONS
MIN. TYP. MAX. UNITS
-
-
1.5
-
-
ns
ns
ns
ns
%
CMOS: CL=15pF, 0.1VDD→0.9VDD
TTL: Load=10TTL, 0.4V →2.4V
CMOS: CL=15pF, 0.9VDD→0.1VDD
TTL: Load=10TTL, 2.4V →0.4V
CMOS: CL=15pF @ 0.5VDD
TTL: Load=10TTL @ 1.4V
f0=4MHz, CL=15pF
Output Rise Time (*1)
1.5
-
1.5
-
Output Fall Time (*1)
tf
-
1.5
-
45
45
-
-
-
-
-
-
55
55
100
6
Output Duty Cycle
DUTY
%
Output Disable Delay Time (*1)
Output Enable Delay Time (*1)
Oscillation Start Time (*1)
tplz
tplz
ns
ms
ms
f0=4MHz, CL=15pF
-
tosc_on
f0=4MHz, CL=15pF
-
6
*1: the values are the designed values.
XC2164Ax1A to L (3rd Overtone) <Chip Enable>
(unless otherwise stated, VDD=3.3V or 5.0V, Ta= -30~+80℃)
PARAMETER
SYMBOL
tr
CONDITIONS
MIN. TYP. MAX. UNITS
-
-
1.5
-
-
ns
ns
ns
ns
%
CMOS: CL=15pF, 0.1VDD→0.9VDD
TTL: Load=10TTL, 0.4V →2.4V
CMOS: CL=15pF, 0.9VDD→0.1VDD
TTL: Load=10TTL, 2.4V →0.4V
CMOS: CL=15pF @ 0.5VDD
TTL: Load=10TTL @ 1.4V
f0=20MHz, CL=15pF
Output Rise Time (*1)
1.5
-
1.5
-
Output Fall Time (*1)
tf
-
1.5
-
45
45
-
-
-
-
-
-
55
55
100
6
Output Duty Cycle
DUTY
%
Output Disable Delay Time (*1)
Output Enable Delay Time (*1)
Oscillation Start Time (*1)
tplz
tplz
ns
ms
ms
f0=20MHz, CL=15pF
-
tosc_on
f0=20MHz, CL=15pF
-
6
*1: the values are the designed values.
XC2164Kx1M, T, V (Fundamental) <Output Enable>
(unless otherwise stated, VDD=3.3V or 5.0V, Ta= -30~+80℃)
PARAMETER
SYMBOL
tr
CONDITIONS
MIN. TYP. MAX. UNITS
-
-
1.5
-
-
ns
ns
ns
ns
%
CMOS: CL=15pF, 0.1VDD→0.9VDD
TTL: Load=10TTL, 0.4V →2.4V
CMOS: CL=15pF, 0.9VDD→0.1VDD
TTL: Load=10TTL, 2.4V →0.4V
CMOS: CL=15pF @ 0.5VDD
TTL: Load=10TTL @ 1.4V
f0=4MHz, CL=15pF
Output Rise Time (*1)
1.5
-
1.5
-
Output Fall Time (*1)
tf
-
1.5
-
45
45
-
-
-
-
-
-
55
55
100
10
6
Output Duty Cycle
DUTY
%
Output Disable Delay Time (*1)
Output Enable Delay Time (*1)
Oscillation Start Time (*1)
tplz
tplz
ns
μs
ms
f0=4MHz, CL=15pF
-
tosc_on
f0=4MHz, CL=15pF
-
*1: the values are the designed values.
* The values shown are preliminary so that the values may be changed without a prior announcement.
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