TTP259
Preliminary
TonTouchTM
IICRDATL1[228H]: IIC fast read data low nibble register 1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
RDAT13
R/W
Bit2
RDAT12
R/W
Bit1
RDAT11
R/W
Bit0
RDAT10
R/W
RDAT13~RDAT10: IIC fast read low nibble data 1.
IICRDATH1[229H]: IIC fast read data high nibble register 1 [R/W], default value [0000]
Register
Bit Name
Read/Write
Bit3
RDAT17
R/W
Bit2
RDAT16
R/W
Bit1
RDAT15
R/W
Bit0
RDAT14
R/W
RDAT17~RDAT14: IIC fast read high nibble data 1.
.IIC operation
IIC support normal mode and fast read mode. Normal mode is
compatible to standard IIC bus. Fast read mode is support fast read data, for
reduce CPU wait time.
In normal mode, IIC device address match and completion of one byte of
data transfer, interrupt will occur. It is set at the falling edge of the 9th clock in
normal mode. if master read last data, master does not send acknowledge to
IIC device, it can let IIC device know don’t need to send data, and do dummy
write for release data bus to avoid bus error.
When an interrupt occurs, MCU must first determine the current mode
will be receive or transmit, and then determine whether the command mode
by MAASF flag. Due to the process by software, so before entering the
interrupt will pull low the SCL, to notify the Master waits. In receive mode
when reading IICDATL and the transfer mode when writing IICDATL, the SCL
pull low will be release. The timing as follow:
2015/05/25
Page 45 of 81
Ver: 1.1
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