TTP259
TonTouchTM
Preliminary
S-11. OST time
The system oscillator generates the system control timing for CPU core or
peripheral devices with fixed control phase, so the waveform of oscillator
becomes sensitive to noise, abnormal duty especially fatal for CPU. Any
switching of clock source needs oscillation stable time (OST) to make sure the
oscillation is stable and synchronized with CPU timing phase. The relative OST
for different oscillator with reference value as below table:
OST
System clock(OSCH) Peripheral clock(OSCL)
High speed STOP wakeup
Low speed STOP wakeup
High speed SLEEP wakeup
Low speed SLEEP wakeup
Low speed to High speed
-
-
8
8
-
8
-
8
8
-
PSP[009H]: Peripheral power saving control register [R/W], default value [0---]
Register
Bit Name
Read/write
Bit3
LDOEN
R/W
Bit2
Bit1
Bit0
-
-
-
-
-
-
LDOEN: LDO enable. (0:disable; 1:enable)
The LDO voltage can be select 2.7V, 4.2V by mask option.
LVREN[304H]: LVR enable control register [R/W], default value [---0]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LVREN
R/W
-
-
-
-
-
-
LVREN: Low voltage reset enable. (0:disable, 1:enable)
When write $5 to this address, LVREN is set to 1; write $A, LVREN is clear to 0.
LDOFLAG[21EH]: LDO flag register [R/W], default value [---0]
Register
Bit Name
Read/write
Bit3
Bit2
Bit1
Bit0
LDOFAIL
R/W
-
-
-
-
-
-
LDOFAIL: When VDD voltage is smaller than LDO voltage, LDOFAIL will be set.
This bit can be clear by write 0.
2015/05/25
Page 23 of 81
Ver: 1.1
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