TTP259
Preliminary
TonTouchTM
Read/Write
R/W
R/W
R/W
R/W
PWM2D7~PWM2D4: PWM2 duty middle nibble data.
PWM2H[22FH]: PWM2 duty high nibble data register [R/W], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
PWM2D11 PWM2D10
R/W R/W
Bit2
Bit1
PWM2D9
R/W
Bit0
PWM2D8
R/W
PWM2D11~PWM2D8: PWM2 duty high nibble data.
PW M xEN
Duty
PW M xO
TCP2CNT
CM P
PW M x
TCP2OV
12-bit duty
W R
PW M xL
4-bit duty L
8-bit duty M and H
TM P duty M and H
W R
PW M xH
and
PW M xM
Figure: PWM (TCP2)
PWMxD
PWM duty
Note
All off
0
1
(0 * clock cycle) / TCP2 timer’s period
(1 * clock cycle) / TCP2 timer’s period
(2 * clock cycle) / TCP2 timer’s period
……
2
……
n
((n) * clock cycle) / TCP2 timer’s period
……
……
TCP2D
((TCP2D) * clock cycle) / TCP2 timer’s period
All on
Note: 1. PWMxD can not bigger than TCP2D
2. TCP2 timer’s period = (TCP2D) * clock cycle.
3. PWM can start 0 or start 1 by mask option.
Table: PWM duty
2015/05/25
Page 40 of 81
Ver: 1.1
TTELEC [ TT Electronics ]
