TTP258
TonTouchTM
Preliminary
TPINTC[01EH]: Touchpad interrupt control register [R/W], default value [0000]
TPINTC
Bit Name
Read/Write
Bit3
TPCTIE
R/W
Bit2
TPCMPIE
R/W
Bit1
Bit0
-
-
-
-
TPCMPIE: Capacitor overcharge interrupt enable. (0: disable; 1: enable)
TPCTIE: Duty counter overflow interrupt enable. (0: disable; 1: enable)
TPINTF[01FH]: Touchpad request flag register [R/W], default value [0000]
TPINTF
Bit Name
Read/Write
Bit3
TPCTF
R/W
Bit2
TPCMF
R/W
Bit1
Bit0
-
-
-
-
TPCMPF: Capacitor overcharge’s flag. (0: inactive; 1: active)
TPCTF: Duty counter’s overflow flag. (0: inactive; 1: active)
TPCT0[213H]: Touch pad duty counter & latch data register 0 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT3/CT3
R/W
Bit2
TPCT2/CT2
R/W
Bit1
TPCT1/CT1
R/W
Bit0
TPCT0/CT0
R/W
TPCT3~TPCT0: Duty counter 1st nibble for counter read
CT3~CT0: 1st nibble of reload latch data
TPCT1[214H]: Touch pad duty counter & latch data register 1 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT7/CT7
R/W
Bit2
TPCT6/CT6
R/W
Bit1
TPCT5/CT5
R/W
Bit0
TPCT4/CT4
R/W
TPCT7~TPCT4: Duty counter 2nd nibble for counter read
CT7~CT4: 2nd nibble of reload latch data
TPCT2[215H]: Touch pad duty counter & latch data register 2 [R], default value [xxxx]
Register
Bit Name
Read/Write
Bit3
TPCT11/CT11 TPCT10/CT10
R/W R/W
Bit2
Bit1
TPCT9/CT9
R/W
Bit0
TPCT8/CT8
R/W
TPCT11~TPCT8: Duty counter 3rd nibble for counter read
CT11~CT8: 3rd nibble of reload latch data
Duty counter value= TPCT2*256 +TPCT1*16+TPCT0
The duty counter will be enabled by writing the TPCHS0 register and will set
the TPCTF flag if duty counter overflow. As writing any of the TPCHS0
addresses will reload the 12 bit counters and clear the TPCTF & TPCMPF.
16’/04/06
Page 38 of 44
Ver.: 1.2
TTELEC [ TT Electronics ]
