TTP258
TonTouchTM
Preliminary
3. I/O Pad Cells
The main features of pad cell are including ESD/EFT protection and
general I/O access. A general I/O pad cell can be configured as input with or
without pull-up resistor, or working as a CMOS or NMOS output driver. The input
pad cell must have pull-up resistor for avoiding a floating state when user
doesn’t care or not be used. For concerning the standby current, user can use
data register or I/O control register to fit the application.
. I/O File Register
PAC[012H]: Port A I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
PAC2
R/W
Bit1
PAC1
R/W
Bit0
PAC0
R/W
-
-
PAC2~PAC0: port A I/O control data
PA[013H]: Port A data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
PA2
R/W
Bit1
PA1
R/W
Bit0
PA0
R/W
-
-
PA2~PA0: port A data
PBC[014H]: Port B I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
PBC1
R/W
Bit0
PBC0
R/W
-
-
-
-
PBC1~PBC0: port B I/O control data
PB[015H]: Port B data register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
Bit2
Bit1
PB1
R/W
Bit0
PB0
R/W
-
-
-
-
PB1~PB0: port B data
PCC[016H]: Port C I/O control register [R/W], default value [1111]
Register
Bit Name
Read/Write
Bit3
PCC3
R/W
Bit2
PCC2
R/W
Bit1
PCC1
R/W
Bit0
PCC0
R/W
PCC3~PCC0: port C I/O control data
16’/04/06
Page 33 of 44
Ver.: 1.2
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