UCC5672
APPLICATION INFORMATION (cont.)
with allowance for the 3.3V supply tolerance (+/- 10%), a 1pF to each plane. Each feed-through will add about
unidirectional fusing device and cable drop. In 3.3V 2.5pF to 3.5pF. Enlarging the clearance holes on both
TRMPWR systems, the UCC3918 is recommended in power and ground planes will reduce the capacitance.
place of the fuse and diode. The UCC3918's lower volt- Similarly, opening up the power and ground planes under
age drop allows additional margin over the fuse and di- the connector will reduce the capacitance for
ode, for the far end terminator.
through-hole connector applications. Capacitance will
also be affected by components, in close proximity,
above and below the circuit board.
Layout is critical for Ultra2, Ultra3/Ultra160 and Ultra320
systems. The SPI-2 standard for capacitance loading is
10pF maximum from each positive and negative signal Unitrode multi-mode terminators are designed with very
line to ground, and a maximum of 5pF between the posi- tight balance, typically 0.1pF between pins in a pair and
tive and negative signal lines of each pair is allowed. 0.3pF between pairs. At each L+ pin, a ground driver
These maximum capacitances apply to differential bus drives the pin to ground, while in single ended mode. The
termination circuitry that is not part of a SCSI device, ground driver is specially designed to not effect the ca-
(e.g. a cable terminator). If the termination circuitry is in- pacitive balance of the bus when the device is in LVD
cluded as part of a SCSI device, (e.g., a host adaptor, SCSI or disconnect mode.
disk or tape drive), then the corresponding requirements
Multi-layer boards need to adhere to the 120Ω imped-
are 30pF maximum from each positive and negative sig-
ance standard, including the connectors and feed-
nal line to ground and 15pF maximum between the posi-
throughs. This is normally done on the outer layers with
tive and negative signal lines of each pair.
4 mil etch and 4 mil spacing between runs within a pair,
The SPI-2 standard for capacitance balance of each pair
and balance between pairs is more stringent. The stan-
dard is 0.75pF maximum difference from the positive and
negative signal lines of each pair to ground. An additional
requirement is a maximum difference of 2pF when com-
paring pair to pair. These requirements apply to differen-
tial bus termination circuitry that is not part of a SCSI
device. If the termination circuitry is included as part of a
device, then the corresponding balance requirements are
2.25pF maximum difference within a pair, and 3pF from
pair to pair.
and a minimum of 8 mil spacing to the adjacent pairs to
reduce crosstalk. Microstrip technology is normally too
low of impedance and should not be used. It is designed
for 50Ω rather than 120Ω differential systems. Careful
consideration must be given to the issue of heat manage-
ment. A multi-mode terminator, operating in SE mode,
will dissipate as much as 130mW of instantaneous power
per active line with TRMPWR = 5.25V. The UCC5672 is
offered in a 28 pin TSSOP. This package includes two
heat sink ground pins. These heat sink/ground pins are
directly connected to the die mount paddle under the die
and conduct heat from the die to reduce the junction tem-
perature. Both of the HS/GND pins need to be connected
to etch area or four feed-through per pin connecting to
the ground plane layer on a multi-layer board.
Feed-throughs, through-hole connections, and etch
lengths need to be carefully balanced. Standard
multi-layer power and ground plane spacing add about
6
TI [ TEXAS INSTRUMENTS ]
