UCC28070-Q1
SLUSA71A –JULY 2010–REVISED JUNE 2011
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Programming the PWM Frequency and Maximum Duty-Cycle Clamp
The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through
the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor
(RRT) directly sets the PWM frequency (fPWM).
7500
R kW =
RT ( )
f
kHz
PWM ( )
(3)
(4)
Once RRT has been determined, the DMAX resistor (RDMX) may be derived.
RDMX = R ´ 2´ D
(
RT
-1
)
MAX
where DMAX is the desired maximum PWM duty-cycle.
Frequency Dithering (Magnitude and Rate)
Frequency dithering refers to modulating the switching frequency to achieve a reduction in conducted-EMI noise
beyond the capability of the line filter alone. The UCC28070 implements a triangular modulation method which
results in equal time spent at every point along the switching frequency range. This total range from minimum to
maximum frequency is defined as the dither magnitude, and is centered around the nominal switching frequency
fPWM set with RRT. For example, a dither magnitude of 20 kHz on a nominal fPWM of 100 kHz results in a
frequency range of 100 kHz ±10 kHz. Furthermore, the programmed duty-cycle clamp set by RDMX remains
constant at the programmed value across the entire range of the frequency dithering.
The rate at which fPWM traverses from one extreme to the other and back again is defined as the dither rate. For
example, a dither rate of 1 kHz would linearly modulate the nominal frequency from 110 kHz to 90 kHz to 110
kHz once every millisecond. A good initial design target for dither magnitude is ±10% of fPWM. Most boost
components can tolerate such a spread in fPWM. The designer can then iterate around there to find the best
compromise between EMI reduction, component tolerances, and loop stability.
The desired dither magnitude is set by a resistor from the RDM pin to GND, of value calculated by the following
equation:
937.5
R kW =
RDM ( )
f
kHz
DM ( )
(5)
Once the value of RRDM is determined, the desired dither rate may be set by a capacitor from the CDR pin to
GND, of value calculated by the following equation:
æ
ç
è
ö
÷
ø
RRDM ( kW )
C pF = 66.7´
CDR ( )
fDR( kHz )
(6)
Frequency dithering may be fully disabled by forcing the CDR pin > 5 V or by connecting it to VREF (6 V) and
connecting the RDM pin directly to GND. (If populated, the relatively high impedance of the RDM resistor may
allow system switching noise to couple in and interfere with the controller timing functions if not bypassed with a
low impedance path when dithering is disabled.)
If an external frequency source is used to synchronize fPWM and frequency dithering is desired, the external
frequency source must provide the dither magnitude and rate functions as the internal dither circuitry is disabled
to prevent undesired performance during synchronization. (See following section for more details.)
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