UC1872
UC2872
UC3872
PIN DESCRIPTIONS
AOUT, BOUT: These outputs provide complementary
drive signals for the push-pull N-channel MOSFETs.
Each one is high for 50% of the time, switching states
each time a zero-detect is sensed.
INV: This pin is the inverting input to the error amplifier
and the input for the open lamp detect circuitry. If the
voltage at INV is below the 1V open lamp detect thresh-
old, the outputs are disabled.
PGND: This pin is the high current ground connection for
the three output drivers.
COMP: COMP is the output terminal of the error ampli-
fier. Compensation components are normally connected
between COMP and INV. Connecting a capacitor from
this pin to ground limits turn on current and blanks the
open lamp detect signal allowing the lamp to start.
REF: This pin is connected to the 3V reference voltage
which is used for the internal logic. Bypass REF to
ground with a 0.01µF ceramic capacitor for proper opera-
tion.
COUT: This output directly drives the bulk regulator
P-channel MOSFET. COUT turn-on is synchronized to
each zero-detect, and therefore switches at twice the fre-
quency of AOUT and BOUT. The modulator controlling
COUT is designed to provide smooth control up to 100%
duty cycle.
VC: VC is the power supply voltage connection for the
output drivers. Bypass it to ground with a 0.1µF ceramic
capacitor for proper operation.
VCC: VCC is the positive supply voltage for the chip. Its
operating range is from 4.2V to 24V. Bypass VCC to
ground with a 0.1µF ceramic capacitor for proper opera-
tion.
CT: A capacitor connected between this pin and GND
ground sets the synchronization frequency range. The
capacitor is charged with approximately 200µA, creating
a linear ramp which is used by COUT’s (buck regulator
driver) PWM comparator.
ZD: The zero-detect input senses when the trans-
former’s primary center tap voltage falls to zero to syn-
chronize the sawtooth voltage waveform on CT. The
threshold is approximately 0.5V, providing a small
amount of offset such that with propagation delay,
zero-volt switching occurs. A resistor (typically 10k)
should be connected between ZD and the primary cen-
ter tap to limit input current at turn off.
ENBL: When ENBL is driven high the device is enabled.
When ENBL is pulled low, the IC is shut down and typi-
cally draws 1µA.
GND: This pin is the ground reference point for the inter-
nal reference and all thresholds.
APPLICATION INFORMATION
Figure 1 shows a complete application circuit using the
UC3872 Resonant Lamp Ballast Controller. The IC pro-
vides all drive, control and housekeeping functions. The
buck output voltage (transformer center-tap) provides the
zero crossing and synchronization signals.
form falls to zero. The actual threshold is 0.5 volts,
providing a small amount of anticipation to offset propa-
gation delay.
The synchronization pulse width is the time required for
the 4mA current sink to discharge the timing capacitor to
0.1 volts. This pulse width limits the minimum linear con-
trol range of the buck regulator. The 200µA current
source charges the capacitor to a maximum of 3 volts. A
comparator blanks the zero detect signal until the capac-
itor voltage exceeds 1 volt, preventing multiple synchro-
nization pulse generation and setting the maximum
frequency. If the capacitor voltage reaches 3 volts (a zero
detection has not occurred) an internal clock pulse is
generated to limit the minimum frequency.
The buck modulator drives a P-channel MOSFET di-
rectly, and operates over a 0-100% duty-cycle range.
The modulation range includes 100%, allowing operation
with minimal headroom.
The oscillator and synchronization circuitry are shown in
Figure 2. The oscillator is designed to synchronize over a
3:1 frequency range. In an actual application however,
the frequency range is only about 1.5:1. A zero detect
comparator senses the primary center-tap voltage, gen-
erating a synchronization pulse when the resonant wave-
4
TI [ TEXAS INSTRUMENTS ]
