SLUS223C – APRIL 1997 – REVISED JUNE 2007
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise stated, these specifications apply for –55°C
≤
T
A
≤
125°C for the UC184X; –40°C
≤
T
A
≤
85°C for the
UC284X; 0°C
≤
T
A
≤
70°C for the 384X; V
CC
= 15 V; R
T
= 10 kΩ; C
T
= 3.3 nF, T
A
= T
J
.
PARAMETER
ERROR AMP SECTION
Input Voltage
Input Bias Current
A
VOL
Unity Gain Bandwidth
PSRR
Output Sink Current
Output Source Current
V
OUT
High
V
OUT
Low
CURRENT SENSE SECTION
Gain
Maximum Input Signal
PSRR
Input Bias Current
Delay to Output
OUTPUT SECTION
Output Low Level
Output High Level
Rise Time
Fall Time
I
SINK
= 20 mA
I
SINK
= 200 mA
I
SOURCE
= 20 mA
I
SOURCE
= 200 mA
T
J
= 25°C, C
L
= 1 nF
T
J
= 25°C, C
L
=
X842/4
X843/5
X842/4
X843/5
X842/3
X844/5
(5)
TEST CONDITIONS
UC1842/3/4/5
UC2842/3/4/5
MIN
TYP
2.50
–0.3
90
1
70
6
–0.8
6
0.7
2.85
3
1
70
–2
–10
300
0.4
2.2
150
0.1
1.5
13
12
13.5
13.5
50
50
15
7.8
9
7.0
95%
46%
16
8.4
10
7.6
97%
48%
150
150
17
9.0
11
8.2
100%
50%
0%
0.5
1
17
1.1
3.15
1.1
MAX
2.55
–1
UC3842/3/4/5
MIN
2.42
65
0.7
60
2
–0.5
5
TYP
2.50
–0.3
90
1
70
6
–0.8
6
0.7
2.85
0.9
3
1
70
–2
150
0.1
1.5
13
12
13.5
13.5
50
50
14.5
7.8
8.5
7.0
95%
47%
16
8.4
10
7.6
97%
48%
150
150
17.5
9.0
11.5
8.2
100%
50%
0%
0.5
11
30
34
1
17
–10
300
0.4
2.2
1.1
3.15
1.1
MAX
2.58
–2
UNIT
V
PIN
1
= 2.5 V
2.45
65
0.7
60
2
–0.5
5
V
µA
dB
MHz
dB
mA
V
2
≤
V
O
≤
4 V
T
J
= 25°C
(5)
12
≤
V
CC
≤
25 V
V
PIN 2
= 2.7 V, V
PIN 1
= 1.1 V
V
PIN 2
= 2.3 V, V
PIN 1
= 5 V
V
PIN
V
PIN
See
V
PIN
2
2
= 2.3 V, R
L
= 15 kΩ to ground
= 2.7 V, R
L
= 15 kΩ to Pin 8
(6) (7)
1
V/V
V
dB
µA
ns
=5V
(6)
(5) (6)
0.9
12
≤
V
CC
≤
25 V
V
PIN
3
= 0 V to 2 V
(5)
V
1nF
(5)
ns
UNDER-VOLTAGE LOCKOUT SECTION
Start Threshold
Min. Operating Voltage After
Turn On
PWM SECTION
Maximum Duty Cycle
Minimum Duty Cycle
TOTAL STANDBY CURRENT
Start-Up Current
Operating Supply Current
V
CC
Zener Voltager
(5)
(6)
(7)
V
PIN 2
= V
PIN 3
= 0 V
I
CC
= 25 mA
30
11
34
mA
V
V
These parameters, although specified, are not 100% tested in production.
Parameter measured at trip point of latch with V
PIN 2
= 0.
A
+
DVPIN
1 , 0
v
VPIN 3
v
0.8 V
DVPIN
3
Gain defined as:
4
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