UC1525A/27A
UC2525A/27A
UC3525A/27A
Regulating Pulse Width Modulators
FEATURES
•
8 to 35V Operation
•
5.1V Reference Trimmed to
±1%
•
100Hz to 500kHz Oscillator Range
•
Separate Oscillator Sync Terminal
•
Adjustable Deadtime Control
•
Internal Soft-Start
•
Pulse-by-Pulse Shutdown
•
Input Undervoltage Lockout with
Hysteresis
•
Latching PWM to Prevent Multiple
Pulses
•
Dual Source/Sink Output Drivers
DESCRIPTION
The UC1525A/1527A series of pulse width modulator integrated circuits are de-
signed to offer improved performance and lowered external parts count when
used in designing all types of switching power supplies. The on-chip +5.1V ref-
erence is trimmed to
±1%
and the input common-mode range of the error ampli-
fier includes the reference voltage, eliminating external resistors. A sync input to
the oscillator allows multiple units to be slaved or a single unit to be synchro-
nized to an external system clock. A single resistor between the C
T
and the dis-
charge terminals provides a wide range of dead-time adjustment. These
devices also feature built-in soft-start circuitry with only an external timing ca-
pacitor required. A shutdown terminal controls both the soft-start circuitry and
the output stages, providing instantaneous turn off through the PWM latch with
pulsed shutdown, as well as soft-start recycle with longer shutdown commands.
These functions are also controlled by an undervoltage lockout which keeps the
outputs off and the soft-start capacitor discharged for sub-normal input volt-
ages. This lockout circuitry includes approximately 500mV of hysteresis for jit-
ter-free operation. Another feature of these PWM circuits is a latch following the
comparator. Once a PWM pulse has been terminated for any reason, the out-
puts will remain off for the duration of the period. The latch is reset with each
clock pulse. The output stages are totem-pole designs capable of sourcing or
sinking in excess of 200mA. The UC1525A output stage features NOR logic,
giving a LOW output for an OFF state. The UC1527A utilizes OR logic which
results in a HIGH output level when OFF.
OS C
VREF OUT
16
4
13
NOR
11
OUTP UT A
VC
BLOCK DIAGRAM
+VIN 15
GROUND 12
S YNC
RT
CT
DIS CHARGE
3
6
Re fe re nce
Re gula tor
To inte rna l
circuitry
UVLO
Lockout
OS C
5
7
Flip
Flop
NOR
14
OUTP UT B
UC1525A Output S ta ge
13
COMP
COMP ENS ATION
INV INP UT
NI INP UT
S OFTS TART
9
1
2
8
3 kΩ
S HUTDOWN 10
OR
14
OUTP UT B
Error
Amp
V
REF
50
µA
S
S
R
P WM
La tch
OR
11
OUTP UT A
VC
5 kΩ
UC1527A Output S ta ge
SLUS191B - February 1997 - Revised June 2005
TI [ TEXAS INSTRUMENTS ]
