UC19431
UC29431
UC39431
UC39431B
PIN DESCRIPTIONS (cont.)
The SENSE pin is also used as the undervoltage lockout
(UVLO). It is intended to keep the chip from operating un-
til the internal reference is properly biased. The thresh-
old is approximately 1V. It is important that once the
UVLO is released, the error amplifier can drive the
transconductance amplifier to stabilize the loop. If a ca-
pacitor is connected between the SENSE and COMP
pins to create a pole, it will limit the slew rate of the error
amplifier. To increase the bandwidth and ensure startup
at low load current, it is recommended to create a zero
along with the pole as shown in the shunt regulator appli-
cation. The error amplifier must slew 2.0V to drive the
transconductance amplifier initially on.
COLL: The collector of the output transistor with a maxi-
mum voltage of 36V. This pin is the output of the
transconductance amplifier. The overall open loop volt-
age gain of the transconductance amplifier is gm • RL,
where gm is designed to be –140mS ±30mS and RL rep-
resents the output load.
COMP: The output of the error amplifier and the input to
the transconductance amplifier. This pin is available to
compensate the high frequency gain of the error ampli-
fier. It is internally voltage limited to approximately 2.0V.
GND: The reference and power ground for the device.
The power ground of the output transistor is isolated on
the chip from the substrate ground used to bias the re-
mainder of the device.
VCC: The power connection for the device. The minimum
to maximum operating voltage is 2.2V to 36.0V. The qui-
escent current is typically 0.50mA.
R1, R2, R3: Connection points to the three internal resis-
tors.
SENSE: The inverting terminal of the error amplifier used
as both the voltage sense input to the error amplifier and
its other compensation point. The error amplifier uses the
SENSE input to compare against the 1.3V on-chip refer-
ence.
UDG-95088
Figure 1. Typical 5.1V shunt regulator application.
3
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