2.11.87 Interrupt Mask 0 Register
Subaddress
Default
7
FIFO THRS
F4h
00h
6
TTX
5
WSS
4
VPS
3
VITC
2
CC F2
1
CC F1
0
Line
FIFO THRS: FIFO threshold passed mask
0 = Disabled (default)
1 = Enabled FIFO_THRES interrupt
TTX: Teletext data available mask
0 = Disabled (default)
1 = Enabled TTX available interrupt
WSS: WSS data available mask
0 = Disabled (default)
1 = Enabled WSS available interrupt
VPS: VPS data available mask
0 = Disabled (default)
1 = Enabled VPS available interrupt
VITC: VITC data available mask
0 = Disabled (default)
1 = Enabled VITC available interrupt
CC F2: CC field 2 data available mask
0 = Disabled (default)
1 = Enabled CC_field 2 available interrupt
CC F1: CC field 1 data available mask
0 = Disabled (default)
1 = Enabled CC_field 1 available interrupt
Line: Line number interrupt mask
0 = Disabled (default)
1 = Enabled Line_INT interrupt
See also the interrupt mask 1 register at subaddress F5h (see Section 2.11.88).
The host interrupt mask 0 and 1 registers can be used by the external processor to mask unnecessary interrupt
sources for the interrupt status 0 and 1 register bits, and for the external interrupt pin. The external interrupt is
generated from all nonmasked interrupt flags.
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TI [ TEXAS INSTRUMENTS ]
