Where F
PLL
is the frequency of the subcarrier PLL, F
ctrl
is the 23-bit PLL frequency control word, and F
sclk
is two times
the pixel frequency. This information can be generated on the GLCO terminal in two formats. The selection between
the two modes is controlled by the GLCO/RTC register at I
2
C subaddress 31h (see Section 2.11.35). Figure 2−19
shows the detail timing diagrams of each mode.
In the GLCO mode, the upper 22 bits of the frequency control word are used. The user can program the subcarrier
PLL phase reset bit that is sent on the next scan line on GLCO. The active low reset bit occurs 7 DATACLKs (2x the
pixel clock) after the transmission of the last bit of PLL frequency control. Upon the transmission of the reset bit, the
phase of the TVP5146 internal subcarrier PLL is reset to zero. A genlocking slave device can be connected to the
GLCO terminal and uses the information on GLCO to synchronize its internal color phase PLL. The clock rate of RTC
is 4 times slower than the GLCO clock rate.
GLCO
M
S
B
22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
L
S
B
0
R
>128 DATACLK
23 DATACLK
23-Bit Frequency Control
1 DATACLK
Start
Bit
Valid
Sample
Reserved
RTC
M
S
B
22
L
S
B
0
S
R
7 DATACLK
1 DATACLK
Invalid
Sample
128 CLK
18 CLK
1 CLK
45 CLK
23-Bit Fsc PLL Increment
3 CLK
Start
Bit
NOTE: RTC Reset bit (R) is active low, Sequence bit (S) PAL:1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no change
Figure 2−19. GLCO and RTC Timing
2.5 Output Formatter
The output formatter sets how the data is formatted for output on the TVP5146 output buses. Table 2−1 shows the
available output modes.
2−10
TI [ TEXAS INSTRUMENTS ]
