TUSB1310A
SLLSE32D–NOVEMBER 2010–REVISED MAY 2011
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Load capacitance (CLOAD) of the crystal varying with the crystal vendors is the total capacitance value of
the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and
CL2 in Figure 5-4. The trace length between the decoupling capacitors and the corresponding power pins
on the TUSB1310A needs to be minimized. It is also recommended that the trace length from the
capacitor pad to the power or ground plane be minimized.
VDDO1P1
VDD1P1
CL1
XI
·
·
VSSOSC
·
Crystal
XO
VDDO1P8
VSSO
CL2
VDD1P8
Figure 5-4. Typical Crystal Connections
5.2 Clock Source Requirements
5.2.1 Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the
transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing
system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock
detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter
reference clock is required to achieve compliance with supported USB3.0 standards. For example,
USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random
phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of
additional jitter components, the Reference Clock jitter must be considerably below the overall jitter
budget.
5.2.2 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
Table 5-1. Oscillator Specification
PARAMETER
Frequency tolerance
Frequency stability
Rise/Fall time
MIN
TYP
MAX
±50
±50
6
UNITS
ppm
CONDITION
Operational temperature
1 year aging
ppm
nsec
20% - 80%
Reference clock RJ
0.8
psec
with JTF (1 sigma)(1)(2)
(1) Sigma value assuming Gaussian distribution
(2) After application of JTF
30
DESIGN GUIDELINES
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