TUSB1310A
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SLLSE32D–NOVEMBER 2010–REVISED MAY 2011
4.2.6 USB Interrupt Enable Falling (10h-12h)
Address: 10-12h (Read), 10h (Write), 11h (Set), 12h (Clear)
Table 4-8. USB Interrupt Enable Falling
BITS
NAME
ACCESS
RESET
DESCRIPTION
Generate an interrupt event notification when Host-disconnect
changes from high to low. Applicable only in host.
0
Hostdisconnect Fall
Rd/Wr/S/C
1b
4.2.7 USB Interrupt Status (13h)
Address: 13h (Read-only)
Table 4-9. USB Interrupt Status
BITS
NAME
ACCESS
Rd/Wr/S/C
RESET
DESCRIPTION
Generate an interrupt event notification when Host-disconnect
changes from high to low. Applicable only in host.
0
Hostdisconnect Fall
1b
4.2.8 USB Interrupt Latch (14h)
Address: 14h (Read-only with auto-clear)
Table 4-10. USB Interrupt Latch
BITS
NAME
ACCESS
RESET
DESCRIPTION
Set to 1b by the PHY when an unmasked event occurs on
Hostdisconnect. Cleared when this register is read.
Applicable only in host mode.
0
Hostdisconnect Fall
Rd/Wr/S/C
1b
4.2.9 Debug (15h)
Address: 15h (Read-only)
Table 4-11. Debug
BITS
NAME
ACCESS
Rd
RESET
DESCRIPTION
0
1
LineState0
LineState1
Reserved
0
0
0
Contains the current value of LineState0
Contains the current value of LineState1
Reserved
Rd
7:2
Rd
4.2.10 Scratch Register (16-18h)
Address: 16-18h (Read), 16h (Write), 17h (Set), 18h (Clear)
Table 4-12. Scratch Register
BITS
NAME
ACCESS
RESET
DESCRIPTION
Empty register byte for testing purposes. Software can read,
write, set, and clear this register and the TUSB1310A
functionality will not be affected.
7:0
Scratch
Rd/Wr/S/C
00
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