TUSB1310A
SLLSE32D–NOVEMBER 2010–REVISED MAY 2011
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4.2.3 Interface Control (07h-09h)
Address: 07-09h (Read), 07h (Write), 08h (Set), 09h (Clear)
Table 4-5. Interface Control
BITS
NAME
ACCESS
Rd
RESET
0b
DESCRIPTION
Reserved, only write a 0 to this bit.
0
1
2
Reserved
Reserved
Reserved
Rd
0b
Reserved, only write a 0 to this bit.
Reserved
Rd
0h
Active low clock suspend. Valid only in Serial Mode. Powers
down the internal clock circuitry only. Valid only when
SuspendM = 1. The TUSB1310A must ignore ClockSuspend
when SuspendM = 0. By default, the clock will not be
powered in Serial Mode.
3
ClockSuspendM
Reserved
Rd/Wr/S/C
0b
0 : Clock will not be powered in Serial Mode
1 : Clock will be powered in Serial Mode
6:4
7
Rd
0h
0
Reserved
Controls internal pullups and pulldowns on the ULPI_STP and
the ULPI_DATA for protecting the ULPI when the Link Layer
Controller tri-states the signals.
Interface
Protect Disable
Rd/Wr/S/C
0 Enables the pullup and pulldown
1 Disables the pullup and pulldown
4.2.4 OTG Control
Address: 0Ah-0Ch (Read), 0Ah (Write), 0Bh (Set), 0Ch (Clear). Controls UTMI+ OTG functions of the
PHY.
Table 4-6. OTG Control Register
BITS
NAME
ACCESS
RESET
DESCRIPTION
0
Reserved
Rd
0b
This bit is not implemented and returns a 0b when read.
Enables the 15-kΩ pull-down resistor on D+.
0 Pull-down resistor not connected to D+
1 Pull-down resistor connected to D+
1
DpPulldown
Rd/Wr/S/C
1b
Enables the 15-kΩ pull-down resistor on D-.
0 Pull-down resistor not connected to D-
1 Pull-down resistor connected to D-
2
DmPulldown
Reserved
Rd/Wr/S/C
Rd
1h
0h
7:3
These bits are not implemented and return zeros when read.
4.2.5 USB Interrupt Enable Rising (0Dh-0Fh)
Address: 0D-0Fh (Read), 0Dh (Write), 0Eh (Set), 0Fh (Clear)
Table 4-7. USB Interrupt Enable Rising
BITS
NAME
ACCESS
RESET
DESCRIPTION
Generate an interrupt event notification when Hostdisconnect
changes from low to high Applicable only in host mode
(DpPulldown and DmPulldown both set to 1b).
0
Hostdisconnect Rise
Rd/Wr/S/C
1b
26
REGISTERS
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