TPS929160-Q1
ZHCSNG0 – APRIL 2023
www.ti.com.cn
7.6 Register Maps
CAUTION
All the RESERVED bits in register are set to 0b in TI manufacture. All the RESERVED bits in regester must be written to 0b in case of
unavoidable register writing.
表 7-18. Register Map
EEPROM
DEFAULT
ADDR
NAME
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
DEFAULT
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
PWMMA0
PWMMA1
PWMMB0
PWMMB1
PWMMC0
PWMMC1
PWMMD0
PWMMD1
PWMME0
PWMME1
PWMMF0
PWMMF1
PWMMG0
PWMMG1
PWMMH0
PWMMH1
PWMMR0
PWMMR1
PWMMR2
PWMMR3
PWMMR4
PWMMR5
PWMMR6
PWMMR7
PWMOUTA0
PWMOUTA1
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
PWMOUTB0
PWMOUTB1
PWMOUTC0
PWMOUTC1
PWMOUTD0
PWMOUTD1
PWMOUTE0
PWMOUTE1
PWMOUTF0
PWMOUTF1
PWMOUTG0
PWMOUTG1
PWMOUTH0
PWMOUTH1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
20h
PWMLA0
RESERVED
RESERVED
RESERVED
RESERVED
PWMLOWOUTA0
00h
0Fh
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
54
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