TPS929160-Q1
ZHCSNG0 – APRIL 2023
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Writing FORCEFS to 1 to force TPS929160-Q1 into FAIL-SAFE state.
Writing EEPLOAD to 1 to load all corresponding EEPROM content.
Writing REGDEFAULT to 1 to reset all registers to default code.
Writing EEPMODE to 1 to enter EEPROM program state.
The register IP name CTRL and FLAG with address between 90h to 98h and A0h to approximately AFh, have
no corresponding EEPROM cells. These registers always set to manufacture default value by the following
operation:
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The TPS929160-Q1 starts from POR.
The TPS929160-Q1 restarts from EN toggled.
The TPS929160-Q1 restarts from VBAT or LDO UVLO triggered.
表 7-17. Registers Default Value Table
POR Default
Register IP Name Register Address
and
REGDEFAULT
EEPLOAD
FAIL-SAFE state
EEPMODE
SOFTRESET
BRT (PWMMx)
00h~17h
20h~37h
40h~44h
50~67h
00h
00h
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Only reset 93h to
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
BRT (PWMLx)
BRT
00h
00h
00h
00h
IOUT
Load EEPROM
Load EEPROM
Load EEPROM
Load EEPROM
CONF
70h~87h
Manufacture
default
CTRL
FLAG
90h~98h
A0~AFh
No action
No action
No action
default, no action Set 93h to 00h
on other registers
Only clear
Manufacture
default
FLAG_POR to 0h
and no action on
other registers
No action
No action
7.5.4 EEPROM Programming
The TPS929160-Q1 has a user-programmable EEPROM with high reliability for automotive applications. All the
EEPROM registers can be burnt through writing the target data into its corresponding register. The TPS929160-
Q1 supports two solutions for individual chip selection through pulling the REF pin high or through device
address configuration by address pin.
7.5.4.1 Chip Selection by Pulling REF Pin High
The TPS929160-Q1 supports using REF pin as chip-select during EEPROM programming. Considering multiple
TPS929160-Q1 devices connected on one FlexWire bus before burning EEPROM, the slave address for all
TPS929160-Q1 are all same before programming in case internal EEPROM register DEVADDR is used for
slave address setup. The EEPROM burning instruction can be sent to target TPS929160-Q1 by pulling the
REF pin of the target TPS929160-Q1 to 5 V. After the REF pin is pulled up to 5 V, the TPS929160-Q1 ignores
the device address setup by ADDR3/ADDR2/ADDR1/ADDR0 pins or EEPROM programmed device address in
EEP_DEVADDR. The master controller must send out data to target TPS929160-Q1 with device address as 0h
and not in broadcast mode.
7.5.4.2 Chip Selection by ADDR Pins Configuration
The TPS929160-Q1 also supports using configuration on ADDR3/ADDR2/ADDR1/ADDR0 pins to determine
the slave address for TPS929160-Q1 if multiple TPS929160-Q1 devices are connected on the same FlexWire
interface. TI recommends to use this approach for applications of multiple TPS929160-Q1 in the same FlexWire
interface. The master controller can send out register data to target TPS929160-Q1 with device address
matched to the ADDR3/ADDR2/ADDR1/ADDR0 pins configuration and not in broadcast mode.
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
50
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