TPS929160-Q1
ZHCSNG0 – APRIL 2023
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SYNC
RX
DEV_ADDR
REG_ADDR
CRC
DATA_1
DATA_N
CRC
TX
图 7-19. Multiple Data Bytes Read in Burst Mode
7.5.2 Registers Lock
The TPS929160-Q1 provides registers content lock feature to prevent unintended modification of registers.
There are four register lock bits for different type of registers covering all registers as the below table illustrates.
TI recommends locking the register after register writing operations.
表 7-16. Registers Lock Table
Register IP Name
BRT (PWMMx)
Address
Lock Register Name
Lock Register Default
00h~17h
20h~37h
40h~44h
50h~67h
70h~83h
84h~87h
90h and 91h
92h~95h
96h
BRT (PWMLx)
BRT
BRTLOCK
0 (unlock)
IOUT
IOUTLOCK
CONFLOCK
1 (lock)
1 (lock)
CONF
CONF
Always locked except in EEPROM program state
No Lock Register
CTRL (ADCCH and CLR)
CTRL
Unlock by sending serial code to CTRLGATE register
No Lock Register
CTRL (CTRLGATE)
CTRL (EEP)
CTRL (EEPGATE)
97h
Unlock by sending serial code to EEPGATE register
No Lock Register
98h
The below instruction is required to access and exit the CTRL (92h to 95h) register.
•
•
•
Write 43h, 4Fh, 44h, 45h to 8-bit register CTRLGATE one-byte by one-byte sequentially to access.
Write any 8-bit data to register CTRLGATE to exit active mode of the CTRL register.
Write any data to register CTRLGATE also reset LOCK register (93h) to default value.
The below instruction is required to access and exit the EEP (97h) register.
•
•
Write 00h, 04h, 02h, 09h, 02h, 09h to 8-bit register EEPGATE one-byte by one-byte sequentially to access.
Keep accessible state until write any 8-bit data to register EEPGATE to exit.
7.5.3 Register Default Data
The TPS929160-Q1 has three types of registers. The register IP name BRT with address between 00h to 17h,
20h to 37h and 40h to 44h, have the same set of EEPROM. These registers reset to 00h from POR, EN toggling
or setting 1 to REGDEFAULT, and they load the code from the corresponding EEPROM value by the following
operations:
•
•
•
•
The TPS929160-Q1 enters FAIL-SAFE state by watchdog timer overflow.
Writing FORCEFS to 1 to force TPS929160-Q1 into FAIL-SAFE state.
Writing EEPLOAD to 1 to load all corresponding EEPROM content.
Writing EEPMODE to 1 to enter EEPROM program state.
The register IP name IOUT and CONF with address between 50h to approximately 67h and 70h to
approximately 87h, have the same set of EEPROM. These registers always load EEPROM value by the
following operation:
•
•
•
•
The TPS929160-Q1 starts from POR.
The TPS929160-Q1 restarts from EN toggled.
The TPS929160-Q1 restarts from VBAT or LDO UVLO triggered.
The TPS929160-Q1 enters FAIL-SAFE state by watchdog timer overflow.
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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