TPS929160-Q1
ZHCSNG0 – APRIL 2023
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Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ST
1
1
1
0
1
0
1
0
SP
ST
0
1
0
1
0
0
0
1
SP
RX
REG_ADDR Frame
0x57
Data Frame N
0x8A
图 7-16. Address and Data Bytes
7.5.1.7 Data Frame
The data bytes, data frame follows the register address byte. The TPS929160-Q1 supports single-data-byte, or
multiple-data-byte writing in one time data transaction. The number of data byte is defined in the device address
byte as introduced in 表 7-12. There are four options including 1 data byte, 4, 16, or 24 data bytes.
表 7-14. DATA Byte
BIT
FIELD
DESCRIPTION
0 - 7
DATA
Data
7.5.1.8 CRC Frame
The CRC data byte follows the data byte as the final byte in the end of one data transaction to ensure the
TPS929160-Q1 correctly receiving all the data bytes from master controller. The master controller must calculate
the CRC value for all bytes binary code including device address byte, register address byte, data bytes and
sends it to TPS929160-Q1 to end the one time communication. The TPS929160-Q1 receives all bytes data,
calculates the CRC and compares the calculated CRC code with received CRC code. If two CRC codes do
not match each other, the TPS929160-Q1 ignores the data transaction and waits for the next data transaction
without reset FlexWire watchdog timer, WDTIMER. The CRC algorithm is the same to the EEPROM CRC
diagnostics as described in EEPROM CRC Error in NORMAL state. The initial code for CRC is FFh as well.
表 7-15. CRC Byte
BIT
FIELD
DESCRIPTION
0 - 7
CRC
CRC Residual
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ST
0
0
0
1
0
1
0
1
SP
RX
CRC
0xA8
图 7-17. CRC Byte
7.5.1.9 Burst Mode
The TPS929160-Q1 with FlexWire protocol supports burst mode for multiple data bytes writing and reading in
one data transaction cycle to accelerate the communication between the master controller and slaves. 图 7-18
shows the data format for multiple data bytes write, and 图 7-19 shows the data format for multiple data bytes
read. The DATA_1 is written to the register in REG_ADDR address, and the following DATA_2 to DATA_N are
written to the registers in REG_ADDR+1 to REG_ADDR+N address sequentially for multiple bytes write. For
multiple data read, the DATA_1 is read from the register in REG_ADDR address, and the following DATA_2 to
DATA_N are read from the registers in REG_ADDR+1 to REG_ADDR+N address sequentially.
SYNC
DEV_ADDR
REG_ADDR
DATA_1
DATA_N
CRC
RX
STATUS
CRC
TX
图 7-18. Multiple Data Bytes Write in Burst Mode
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
48
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