TPS929160-Q1
ZHCSNG0 – APRIL 2023
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7.5.1.3 Status Response
When the TPS929160-Q1 as a slave device receives a non-broadcast frame, it first verifies the CRC byte. After
CRC check is succeeded, the TPS929160-Q1 sends out the device status of FLAG_ERR register byte followed
by CRC byte. The response is disabled by setting register ACKEN to 0. The response sent from TPS929160-Q1
is enabled by default.
Every communication requires CRC verification to make sure the integrity for the data transaction. In broadcast
mode, TPS929160-Q1 does not send out a response.
7.5.1.4 Synchronization Byte
The first byte data sent from master controller to TPS929160-Q1 is synchronization frame (SYNC). The master
controller sends the clock signal to TPS929160-Q1 through outputting 01010101 binary code in first frame.
The TPS929160-Q1 adaptively uses the same clock to communicate with master by synchronization of internal
high frequency clock. To avoid clock drift over time, the synchronization byte is always required for each new
instruction transaction on FlexWire interface. With this approach, the communication reliability is improved, and
the cost for external crystal oscillator is saved. 图 7-15 is the timing diagram for synchronization frame and
device address frame.
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
ST
1
0
1
0
1
0
1
0
SP
ST
0
0
0
1
0
0
0
1
SP
RX
Sync Frame
0x55
DEV_ADDR Frame
0x88
图 7-15. Synchronization Byte
7.5.1.5 Device Address Byte
The device address byte, DEV_ADDR frame follows the SYNC frame. There are total 8 bits binary code in
the device address byte. The below table provides detailed definition for each bit function. The DEVICE_ADDR
register is required to set to 0000b for broadcast mode, otherwise the broadcast mode cannot be enabled. The
broadcast mode is only effective for writing mode. The READ/WRITE bit must be 1 for broadcast mode.
表 7-12. DEV_ADDR Byte
BIT
FIELD
DESCRIPTION
3-0
DEVICE_ADDR
Target device address
00b: Single-byte mode with 1 byte of data; 01b: Bust mode with 4 bytes of data;
10b: Burst mode with 16 bytes of data; 11b: Burst mode with 24 bytes of data
5-4
DATA_LENGTH
6
7
BROADCAST
READ/WRITE
Broadcast mode. 1: Broadcast (DEVICE_ADDR =0000b); 0: Single-device only
Read / Write mode. 1: Write mode; 0: Read mode
7.5.1.6 Register Address Byte
The register address byte, REG_ADDR frame follows the device address frame. There are total 8 bits binary
code in register address byte. The maximum allowed register address is 255. The below figure is the timing
diagram for register address frame and data frame.
表 7-13. REG_ADDR Byte
BIT
FIELD
DESCRIPTION
0 - 7
REG_ADDR
Register address
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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