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TPS929160QDCPRQ1 参数 Datasheet PDF下载

TPS929160QDCPRQ1图片预览
型号: TPS929160QDCPRQ1
PDF下载: 下载PDF文件 查看货源
内容描述: [汽车级 16 通道 40V 高侧 LED 和 OLED 驱动器 | DCP | 38 | -40 to 125]
分类和应用: 驱动驱动器
文件页数/大小: 127 页 / 8604 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS929160-Q1  
ZHCSNG0 – APRIL 2023  
www.ti.com.cn  
7-10. Frame-Byte Description  
BYTE NAME  
SYNC  
LENGTH (byte)  
DESCRIPTION  
Synchronization byte from master  
Device address bit, r/w, broadcast, burst mode  
Register address  
1
DEV_ADDR  
REG_ADDR  
DATA_N  
1
1
Variable (1, 4, 16, 24)  
N-th byte data content  
Cyclic redundancy check (CRC) for DEV_ADDR, REG_ADDR and all  
DATA bytes  
CRC  
1
1
STATUS  
Acknowledgment (Return FLAG_ERR register value)  
7.5.1.2 UART Interface Address Setting  
Each FlexWire bus supports maximum 16 slave devices. The TPS929160-Q1 has three pinouts including  
ADDR3, ADDR2, ADDR1, and ADDR0 for slave address configuration. There are additional 4-bit EEPROM  
register to program the slave address of the TPS929160-Q1. The register INTADDR sets the device slave  
address by either address pins setup or internal EEPROM register code.  
If INTADDR is 1, the device uses the binary code in register DEVADDR[3:0] as slave address as shown in the  
below table.  
If INTADDR is 0, the device uses external inputs on ADDR3, ADDR2, ADDR1 and ADDR0 as shown in 7-11  
and ignore DEVADDR[3:0] code.  
The address 0h to Fh can be used as slave address for up to 16 pieces of TPS929160-Q1 in the same  
FlexWire bus. Do not have two TPS929160-Q1 sharing the same slave address either setting by internal register  
DEVADDR or address pins configuration on ADDR3, ADDR2, ADDR1 and ADDR0.  
The default value for DEVADDR[3:0] is 0h.  
7-11. Device Address Setting  
INTERNAL ADDRESS SETTING  
BIT2 BIT1  
DEVADDR[3] DEVADDR[2] DEVADDR[1] DEVADDR[0]  
EXTERNAL ADDRESS SETTING  
Address(HEX)  
BIT3  
BIT0  
BIT3  
BIT2  
BIT1  
BIT0  
ADDR3  
ADDR2  
ADDR1  
ADDR0  
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Copyright © 2023 Texas Instruments Incorporated  
English Data Sheet: SLVSG60  
46  
Submit Document Feedback  
Product Folder Links: TPS929160-Q1  
 
 
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