TPS929160-Q1
ZHCSNG0 – APRIL 2023
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7.5 Programming
7.5.1 FlexWire Protocol
7.5.1.1 Protocol Overview
The FlexWire is a UART-based protocol supported by most microcontroller units (MCU). Each frame contains
multiple bytes started with a synchronization byte. The synchronization byte allows LED drivers to synchronize
with master MCU frequency, therefore saving the extra cost on high precision oscillators that are commonly used
in UART / CAN interfaces. Each byte has 1 start bit, 8 data bits, 1 stop bit, no parity check. The LSB data follows
the start bit as the below figure describes. The FlexWire supports adaptive communication frequency ranging
from 10 kHz to 1 MHz. The protocol supports master-slave with star-connected topology.
Start
Stop
Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7
图 7-12. One Byte Data Structure
The FlexWire is designed robust for automotive environment. After the slave device receives a communication
frame, it firstly verifies its CRC byte. Only when CRC is verified, the slave device sends out response frame
and clears the watchdog timer. In addition, if one communication frame is interrupted in the middle without any
bus toggling for a period longer than timeout timer t(DBWTIMER), the TPS929160-Q1 resets the communication
and waits for next communication starting from synchronization byte. It is also required for idle period between
bytes within t(DBWTIMER). The timeout timer t(DBWTIMER) is programmable by configuration register DBWTIMER. TI
recommends using a longer timeout setting for low baud rate communication to avoid unintended timeout and
using a shorter timeout setting for high baud rate communication.
If communication CRC check fails, the TPS929160-Q1 ignores the message without sending the feedback. The
master does not receive any feedback if the communication is unsuccessful. In this case, the communication can
be reset by keeping communication bus idle for t(DBWTIMER), which forces the TPS929160-Q1 to clear its cache
and be ready for new communication.
FlexWire supports both write and readback. Both write or readback communication supports burst mode for high
throughput and single-byte mode. 图 7-13 describes the frame structure of a typical single-byte write action. The
master frame consists of SYNC, DEV_ADDR, REG_ADDR, DATA and CRC bytes. After CRC is verified, the
slave immediately feeds back ACK byte. 图 7-14 describes the frame structure of a typical single-byte readback
action. The master frame consists of SYNC, DEV_ADDR, REG_ADDR, and CRC bytes. After CRC is verified,
the slave immediately feeds back DATA and ACK bytes.
SYNC
DEV_ADDR
REG_ADDR
DATA
CRC
RX
STATUS
CRC
TX
图 7-13. Single-Byte Write Command with Status Feedback
SYNC
DEV_ADDR
REG_ADDR
CRC
RX
TX
DATA
CRC
图 7-14. Single-Byte Readback Command
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Product Folder Links: TPS929160-Q1
English Data Sheet: SLVSG60
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