TPS929160-Q1
ZHCSNG0 – APRIL 2023
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V(SLSTH0) is selected for current OUTXn when LSTHOUTXn is set to 0, however V(SLSTH1) is selected when
SLSLTHOUTXn is set to 1. The actual voltage value for V(SLSTH0) and V(SLSTH1) is programmable by two 8-bit
registers SLSTH0 and SLSTH1 from 2.5 V to 34.375 V at 125-mV interval. In FAIL-SAFE state, the TPS929160-
Q1 shuts down the normal current regulation and PWM duty cycle for the faulty output, then the device sources
a pulse current, I(OUTXn) programed by IOUTXn register to the faulty output every t(SLS_Retry), 10 ms for retrying.
When the voltage V(OUTXn) of error output rises above threshold V(SLSTHx) + 275 mV with duration longer than
t(BLANK) + t(SLS_deg) during retrying, or the supply voltage V(SUPPLY) is below the threshold V(LOWSUPTH), the device
automatically resumes the normal current and PWM dutycycle setup and releases the ERR pin.
The fault is latched in flag registers. When the single-LED short-circuit fault is removed, the master controller
must write 1 to register CLRFAULT to clear FLAG_SLSOUTXn, FLAG_OUT and FLAG_ERR. The CLRFAULT
automatically returns to 0.
7.3.8.11 EEPROM CRC Error in FAIL-SAFE state
The TPS929160-Q1 automatically reloads all EEPROM code into the corresponding configuration registers
every time after entering the FAIL-SAFE state. The TPS929160-Q1 implements a EEPROM CRC check after
loading the EEPROM code to configuration register in FAIL-SAFE state. The calculated CRC results are sent
to register CALC_EEPCRC and compared to the data in EEPROM register EEPCRC, which stores the CRC
code for all EEPROM registers except for DIM-R reserved register. The reserved DIM-R register value is not
included in the EEPCRC calculation. The TPS929160-Q1 EEPROM configuration tool are available on ti.com to
help calculate the EEPCRC value. If the code in register CALC_EEPCRC is not matched to the code in register
EEPCRC, the TPS929160-Q1 turns off all channels output, pulls the ERR pin down with constant current sink to
report the fault, and sets the registers including FLAG_EEPCRC and FLAG_ERR to 1. The CRC code for all the
EEPROM registers must be burnt into EEPROM register EEPCRC in the end of production line. The CRC code
algorithm is described in EEPROM CRC Error in NORMAL state.
7.3.8.12 Fault Masking in FAIL-SAFE state
The TPS929160-Q1 provides fault masking capability using masking registers. The device is capable of masking
faults by channels or by fault types. The fault masking does not disable diagnostics features but only prevents
fault reporting to FLAG_OUT register, FLAG_ERR register, and ERR output. The below table gives the detailed
description for each fault mask register in NORMAL state.
To disable diagnostics on a single channel in FAIL-SAFE state, burning EEPROM of DIAGENOUTXn registers
to 0 disables open-circuit, LED short-circuit and single-LED short-circuit diagnostics of channel x, and thus no
fault of this channel is reported to FLAG_OPENOUTXn, FLAG_SHORTOUTXn, FLAG_SLSOUTXn, FLAG_OUT
or FLAG_ERR registers, or to the ERR output.
表 7-7. Fault Masking in FAIL-SAFE State
Fault Detected
Mask Register
FLAG Name
ERR PIN
FLAG_LOWSUP = 1
FLAG_ERR = 0
MASKLOWSUP = 1
No action
No action
No action
Low-supply warning
FLAG_LOWSUP = 1
FLAG_ERR = 1
MASKLOWSUP = 0
MASKSUPUV = 1
MASKSUPUV = 0
MASKREF = 1
FLAG_SUPUV = 1
FLAG_ERR = 0
Supply undervoltage
Reference fault
FLAG_SUPUV = 1
FLAG_ERR = 1
Constant pulled down
No action
FLAG_REF = 1
FLAG_ERR = 0
FLAG_REF = 1
FLAG_ERR = 1
MASKREF = 0
Constant pulled down
No action
FLAG_PRETSD = 1
FLAG_ERR = 0
MASKPRETSD = 1
MASKPRETSD = 0
Pre-thermal warning
FLAG_PRETSD = 1
FLAG_ERR = 1
No action
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
38
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