TPS929160-Q1
ZHCSNG0 – APRIL 2023
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internal trim EEPROM error, the FLAG_EEPPAR is set to 1. The master controller can write 1 to REGDEFAULT
to reset all the regiters to default value and reload the EEPROM to corresponding registers in NORMAL state.
Reloading the EEPROM triggers the EEPROM CRC check.
The master controller must write CLRFAULT to 1 to clear the fault flags, and the CLRFAULT bit automatically
returns to 0.
The CRC code for all the EEPROM registers must be burnt into EEPROM register of EEPCRC in the end of
production line. The CRC code algorithm for multiple bytes of binary data is based on the polynomial, X8 + X5 +
X4 + 1. The CRC code contain 8 bits binary code, and the initial value is FFh. As described in the below figure,
all bits code shift to MSB direction for 1 bit with three exclusive-OR calculation. A new CRC code for one byte
input canbe generated after repeating the 1 bit shift and three exclusive-OR calculation for eight times. Based
on this logic, the CRC code can be calculated for all the EEPROM register byte. When the EEPROM design for
production is finalized, the corresponding CRC code based on the calculation must be burnt to EEPROM register
EEPCRC together with other EEPROM registers in the end of production line. If the DC current for each output
channel must be calibrated in the end of production for different LED brightness bin, the CRC code for each
production devices must be calculated independent and burnt during the calibration. The CRC algorithm must be
implemented into the LED calibration system in the end of production line.
XOR
Bit Input
LSB First
CRC
Bit 0
CRC
Bit 1
CRC
Bit 2
CRC
Bit 6
CRC
Bit 5
CRC
Bit 4
CRC
Bit 3
CRC
Bit 7
XOR
XOR
图 7-9. CRC Algorithm Diagram
7.3.7.12 Communication Loss Diagnostic in NORMAL state
The TPS929160-Q1 monitors the FlexWire interface for the communication with an internal watchdog timer.
Any successful non-broadcast communication with correct CRC and address matching target device
automatically resets the timer. If the watchdog timer overflows, device automatically switches to FAIL-SAFE
state and sets the FLAG_FS to 1. The master controller can access the TPS929160-Q1 and write 1 to CLRFS to
set the device to NORMAL state again when the communication recovers.
The watchdog timer is programmable by 4-bit register WDTIMER. The TPS929160-Q1 can directly enter FAIL-
SAFE states from NORMAL state by burning EEPROM of WDTIMER to Fh. Disabling the watchdog timer by
setting WDTIMER to 0h prevents the device from getting into FAIL-SAFE state.
7.3.7.13 Fault Masking in NORMAL state
The TPS929160-Q1 provides fault masking capability using masking registers. The device is capable of masking
faults by channels or by fault types. The fault masking does not disable diagnostics features but only prevents
fault reporting to FLAG_OUT register, FLAG_ERR register, and ERR output. The below table lists the detailed
description for each fault mask register in NORMAL state.
To disable diagnostics on a single channel, setting DIAGENOUTXn registers to 0 disables open-circuit, LED
short-circuit and single-LED short circuit diagnostics of channel x and thus no fault of this channel is reported to
FLAG_OPENOUTXn, FLAG_SHORTOUTXn, FLAG_SLSOUTXn, FLAG_OUT or FLAG_ERR registers, or to the
ERR output.
表 7-5. Fault Masking in NORMAL state
Fault Detected
Mask Register
MASKLOWSUP = 1
MASKLOWSUP = 0
FLAG Name
ERR PIN
FLAG_LOWSUP = 1
FLAG_ERR = 0
No action
Low-supply warning
FLAG_LOWSUP = 1
FLAG_ERR = 1
One pulse pulled down for 50 μs
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSG60
32
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