TPS767D3xx
SLVS209H – JULY 1999 – REVISED AUGUST 2008.........................................................................................................................................................
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TPS767D3xx
V
IN
5
IN
6
IN
OUT
C
1
0.1
m
F
50V
4
EN
OUT
24
23
+
C
OUT
10
m
F
GND
3
RESET
28
RESET
250kW
V
OUT
Figure 1. Typical Application Circuit (Fixed Versions) for Single Channel
TIMING DIAGRAM
V
IN
V
RES
(1)
V
RES
t
V
OUT
V
IT
+
(2)
V
IT
+
(2)
Threshold
Voltage
V
IN
-
Less than 5% of
the output voltage
V
IN
-
t
RESET
Output
200ms
Delay
200ms
Delay
Output
Undefined
t
Output
Undefined
(1)
(2)
V
RES
is the minimum input voltage for a valid RESET.
V
IT
—Trip voltage is typically 5% lower than the output voltage (95% V
OUT
).
6
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