TPS732xx
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SBVS037I–AUGUST 2003–REVISED MAY 2006
APPLICATION INFORMATION
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
The TPS732xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS732xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and
an adjustable output version. All versions have
thermal and over-current protection, including
foldback current limit.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response,
noise rejection, and ripple rejection. A higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the
connections for the adjustable output version
(TPS73201).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
The TPS732xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN - VOUT < 0.5V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50nΩF. Total ESR
includes all parasitic resistances, including capacitor
ESR and board, socket, and solder joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance will meet this requirement.
VIN
VOUT
IN
OUT
TPS732xx
GND
EN
NR
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
OUTPUT NOISE
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS732xx and
it generates approximately 32µVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
FB
TPS732xx
R1
R2
CFB
EN
GND
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
R2
(1)
Optional capacitor
reduces output noise
and improves
(R1 + R2)
×
1.204
VOUT
=
Since the value of VREF is 1.2V, this relationship
reduces to:
R1
transient response.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
Figure 32. Typical Application Circuit for
Adjustable-Voltage Versions
(2)
for the case of no CNR
.
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
For best accuracy, make the parallel combination of
R1 and R2 approximately euqal to 19kΩ. This 19kΩ,
11
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