TPS717xx
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SBVS068E – FEBRUARY 2006 – REVISED MAY 2008
PIN CONFIGURATIONS
TPS717xx DCK
SC70-5 PACKAGE
(TOP VIEW)
IN
GND
EN
1
2
3
4
NR/FB
5
OUT
TPS717xx DRV
2mm x 2mm SON
(TOP VIEW)
OUT
NR/FB
GND
1
2
3
GND
6
5
4
IN
N/C
EN
(1)
TPS717xx DSE
1.5mm x 1.5mm SON
(TOP VIEW)
OUT
GND
NR/FB
1
2
3
6
5
4
IN
N/C
EN
(1)
NOTE: (1) N/C = Not connected.
Table 1. PIN DESCRIPTIONS
TPS717xx
NAME
IN
GND
EN
NR
FB
OUT
NC
SC70
(DCK)
1
2
3
4
4
5
–
2×2 SON
(DRV)
6
3
4
2
2
1
5
1.5×1.5
SON
(DSE)
6
2
4
3
3
1
5
Input to the device.
Ground.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into standby mode, thereby reducing operating current.
Fixed voltage versions only. An external capacitor connected to this terminal bypasses
noise generated by the internal bandgap, lowering output noise.
Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A
resistor divider from OUT to FB sets the output voltage when in regulation.
This is the regulated output voltage. A small capacitor is needed from this pin to ground
to assure stability; a 1.0µF ceramic capacitor is adequate.
Not connected. This pin can be tied to ground to improve thermal dissipation.
DESCRIPTION
Copyright © 2006–2008, Texas Instruments Incorporated
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