TPS65142
SLVSAX5 –JULY 2011
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ELECTRICAL CHARACTERISTICS (continued)
VIN = 3.3 V, VS = 9V, VGH = 20 V, VBAT = 10.8V, IISET = 15µA, VIFBx = 0.5V, EN = VIN, TA = –40°C to 85°C, typical values are at
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOGIC SIGNALS FREQ, VFLK, EN, DCTRL
VIH
VIL
Logic high input voltage
VIN = 2.5 V to 6 V
2.0
V
Logic low input voltage
VIN = 2.5 V to 6 V
0.5
0.1
V
ILKG
Input leakage current of VFLK pin
VFLK = 6 V, FREQ = GND
µA
Pull-down resistance for EN and DCTRL
pins
RPD
EN = DCTRL = 3.3 V
400
800
18
1600
kΩ
AVDD BOOST CONVERTER
VS
Output voltage boost(1)
7
16.9
16.5
19
V
V
VOVP
Overvoltage protection
VS rising
TA = –40°C to 85°C
TA = 25°C
1.226
1.230
1.240 1.254
1.240 1.250
0.1
VFB
Feedback regulation voltage
Feedback input bias current
N-channel MOSFET on-resistance
V
µA
Ω
IFB
VFB = 1.240 V
VIN = VGS = 5 V, ISW = current limit
VIN = VGS = 3.3 V, ISW = current limit
0.13
0.15
0.38
0.44
rDS(ON)
AVDD Boost converter SW leakage
current
ILkg(SW)
ILIM
VIN = 1.8 V, VSW = 17 V, Device not switching
30
µA
VIN = 2.5 V to 6 V
VIN = 2.3 V to 2.5 V
FREQ = high
1.8
1.5
2.5
3.2
A
A
N-Channel MOSFET current limit
0.9
1.2
1.5
MHz
kHz
fBOOST
TSS
Switching frequency
Softstart time
FREQ = low
470
625
780
FREQ = high, L1 = 6.8 µH, CO1 = 2 0µF
and 10 mA load current
2
ms
Line regulation
Load regulation
VIN = 2.5 V … 6 V, IOUT = 10 mA
IOUT = 0 A …500 mA
0.008
0.15
%/V
%/A
VGH REGULATOR
fSWP Switching frequency
0.5 x fBOOST
MHz
V
TA = –40°C to 85°C
TA = 25°C
1.210
1.221
1.240 1.270
1.240 1.259
0.1
VFBP
Reference voltage of feedback
IFBP
Feedback input bias current
DRVP RDS(ON) (PMOS)
DRVP RDS(ON) (NMOS)
VFBP = 1.240 V
µA
Ω
rDS(ON)P1
rDS(ON)N1
VGL REGULATOR
VS = 9 V, I(DRVP) = 40 mA
VS = 9 V, I(DRVP) = –40 mA
8
3
20
10
Ω
fSWN
Switching frequency
0.5 x fBOOST
MHz
V
VREF
Reference voltage
3.05
3.12
0
3.18
48
VFBN
Reference voltage of feedback
Feedback input bias current
DRVN RDS(ON) (PMOS)
DRVN RDS(ON) (NMOS)
–48
mV
µA
Ω
IFBN
VFBN = 0 V
0.1
20
rDS(ON)P2
rDS(ON)N2
VS = 9 V, I(DRVN) = 40 mA
VS = 9 V, I(DRVN) = –40 mA
8
3
10
Ω
GATE VOLTAGE SHAPING VGHM
I(DPM)
Capacitor charge current VDPM pin
17
20
13
13
23
25
25
µA
Ω
rDS(ON)M1
rDS(ON)M2
VGH to VGHM rDS(ON) (M1 PMOS)
VGHM to RE rDS(ON) (M2 PMOS)
VFLK = low, I(VGHM) = 20 mA
VFLK = high, I(VGHM) = 20 mA, VGHM = 7.5 V
Ω
(1) Maximum output voltage limited by the overvoltage protection and not the maximum power switch rating
4
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