TPS54260
SLVSA86 –MARCH 2010
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Layout
Layout is a critical portion of good power supply design. There are several signals paths that conduct fast
changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise
or degrade the power supplies performance. To help eliminate these problems, the VIN pin should be bypassed
to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to
minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the anode of the catch
diode. See Figure 62 for a PCB layout example. The GND pin should be tied directly to the power pad under the
IC and the power pad.
The power pad should be connected to any internal PCB ground planes using multiple vias directly under the IC.
The PH pin should be routed to the cathode of the catch diode and to the output inductor. Since the PH
connection is the switching node, the catch diode and output inductor should be located close to the PH pins,
and the area of the PCB conductor minimized to prevent excessive capacitive coupling. For operation at full rated
load, the top side ground area must provide adequate heat dissipating area. The RT/CLK pin is sensitive to noise
so the RT resistor should be located as close as possible to the IC and routed with minimal lengths of trace. The
additional external components can be placed approximately as shown. It may be possible to obtain acceptable
performance with alternate PCB layouts, however this layout has been shown to produce good results and is
meant as a guideline.
Vout
Output
Capacitor
Output
Inductor
Topside
Ground
Route Boot Capacitor
Catch
Area
Trace on another layer to
provide wide path for
topside ground
Diode
Input
Bypass
Capacitor
BOOT
VIN
PH
GND
Vin
EN
COMP
UVLO
SS/TR
RT/CLK
VSENSE
PWRGD
Compensation
Network
Adjust
Resistor
Divider
Resistors
Slow Start
Capacitor
Frequency
Thermal VIA
Signal VIA
Set Resistor
Figure 62. PCB Layout Example
Estimated Circuit Area
The estimated printed circuit board area for the components used in the design of Figure 49 is 0.55 in2. This area
does not include test points or connectors.
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