TPS54260
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SLVSA86 –MARCH 2010
Under Voltage Lock Out Set Point
The Under Voltage Lock Out (UVLO) can be adjusted using an external voltage divider on the EN pin of the
TPS54260. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power
down or brown outs when the input voltage is falling. For the example design, the supply should turn on and start
switching once the input voltage increases above 6.0 V (enabled). After the regulator starts switching, it should
continue to do so until the input voltage falls below 5.5 V (UVLO stop).
The programmable UVLO and enable voltages are set using the resistor divider of R1 and R2 between Vin and
ground to the EN pin. Equation 2 through Equation 3 can be used to calculate the resistance values necessary.
For the example application, a 124 kΩ between Vin and EN (R1) and a 30.1 kΩ between EN and ground (R2)
are required to produce the 6.0 and 5.5 volt start and stop voltages.
Output Voltage and Feedback Resistors Selection
The voltage divider of R5 and R6 is used to set the output voltage. For the example design, 10.0 kΩ was
selected for R6. Using Equation 1, R5 is calculated as 31.25 kΩ. The nearest standard 1% resistor is 31.6 kΩ.
Due to current leakage of the VSENSE pin, the current flowing through the feedback network should be greater
than 1 mA in order to maintain the output voltage accuracy. This requirement makes the maximum value of R2
equal to 800 kΩ. Choosing higher resistor values will decrease quiescent current and improve efficiency at low
output currents but may introduce noise immunity problems.
Compensation
There are several methods used to compensate DC/DC regulators. The method presented here is easy to
calculate and ignores the effects of the slope compensation that is internal to the device. Since the slope
compensation is ignored, the actual cross over frequency will usually be lower than the cross over frequency
used in the calculations. This method assumes the crossover frequency is between the modulator pole and the
esr zero and the esr zero is at least 10 times greater the modulator pole. Use SwitcherPro software for a more
accurate design.
To get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using Equation 41 and
Equation 42. For Cout, use a derated value of 40 mF. Use equations Equation 43 and Equation 44, to estimate a
starting point for the crossover frequency, fco, to design the compensation. For the example design, fpmod is
1206 Hz and fzmod is 530.5 kHz. Equation 43 is the geometric mean of the modulator pole and the esr zero and
Equation 44 is the mean of modulator pole and the switching frequency. Equation 43 yields 25.3 kHz and
Equation 44 gives 13.4 kHz. Use the lower value of Equation 43 or Equation 44 for an initial crossover frequency.
For this example, a higher fco is desired to improve transient response. the target fco is 35.0 kHz. Next, the
compensation components are calculated. A resistor in series with a capacitor is used to create a compensating
zero. A capacitor in parallel to these two components forms the compensating pole.
Ioutmax
¦p mod =
2 × p × Vout × Cout
1
(41)
¦z mod =
2 ´ p ´ Resr × Cout
(42)
(43)
fco
=
fpmod´ fzmod
fsw
fpmod´
2
fco
=
(44)
To determine the compensation resistor, R4, use Equation 45. Assume the power stage transconductance,
gmps, is 10.5A/V. The output voltage, Vo, reference voltage, VREF, and amplifier transconductance, gmea, are
3.3V, 0.8V and 310 mA/V, respectively. R4 is calculated to be 20.2 kΩ, use the nearest standard value of 20.0
kΩ. Use Equation 46 to set the compensation zero to the modulator pole frequency. Equation 46 yields 4740 pF
for compensating capacitor C5, a 4700 pF is used for this design.
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ø
æ
ç
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÷
ø
2´p ´ fco ´Cout
Vout
Vref ´ gmea
R4 =
´
gmps
(45)
35
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