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SLVS398F – JUNE 2001 – REVISED APRIL 2007
COMPONENT SELECTION
The values for the components used in this design
example were selected using the SWIFT designer
software tool. SWIFT designer provides a complete
design environment for developing dc-dc converters
using the TPS54610.
bypass capacitor connections, the VIN pins, and the
TPS54610 ground pins. The minimum recommended
bypass capacitance is 10-mF ceramic capacitor with
a X5R or X7R dielectric and the optimum placement
is closest to the VIN pins and the PGND pins.
The TPS54610 has two internal grounds (analog and
power). Inside the TPS54610, the analog ground ties
to all of the noise sensitive signals, while the power
ground ties to the noisier power signals. Noise
injected between the two grounds can degrade the
performance of the TPS54610, particularly at higher
output currents. However, ground noise on an analog
ground plane can also cause problems with some of
the control and bias signals. Therefore, separate
analog and power ground traces are recommended.
There is an area of ground on the top layer directly
under the IC, with an exposed area for connection to
the PowerPAD. Use vias to connect this ground area
to any internal ground planes. Additional vias are
also used at the ground side of the input and output
filter capacitors. The AGND and PGND pins are tied
to the PCB ground by connecting them to the ground
area under the device as shown. The only
components that tie directly to the power ground
plane are the input capacitors, the output capacitors,
the input voltage decoupling capacitor, and the
PGND pins of the TPS54610. Use a separate wide
trace for the analog ground signal path. The analog
ground is used for the voltage set point divider,
timing resistor RT, slow-start capacitor and bias
capacitor grounds. Connect this trace directly to
AGND (Pin 1).
The PH pins are tied together and routed to the
output inductor. Since the PH connection is the
switching node, the inductor is located close to the
PH pins. The area of the PCB conductor is
minimized to prevent excessive capacitive coupling.
Connect the boot capacitor between the phase node
and the BOOT pin as shown. Keep the boot
capacitor close to the IC and minimize the conductor
trace lengths.
Connect the output filter capacitor(s) as shown
between the VOUT trace and PGND. It is important
to keep the loop formed by the PH pins, LOUT,
COUT and PGND as small as practical.
Place the compensation components from the VOUT
trace to the VSENSE and COMP pins. Do not place
these components too close to the PH trace. Due to
the size of the IC package and the device pin-out,
they must be routed close, but maintain as much
separation as possible while still keeping the layout
compact.
INPUT FILTER
The input to the circuit is a nominal 5 VDC. The input
filter C2 is a 220-µF POSCAP capacitor, with a
maximum allowable ripple current of 3 A. C8
provides high frequency decoupling of the TPS54610
from the input supply and must be located as close
as possible to the device. Ripple current is carried in
both C2 and C8, and the return path to PGND must
avoid the current circulating in the output capacitors
C9 and C10.
FEEDBACK CIRCUIT
The resistor divider network of R3 and R4 sets the
output voltage for the circuit at 3.3 V. R4, along with
R1, R5, C3, C5, and C6 form the loop compensation
network for the circuit. For this design, a Type 3
topology is used.
OPERATING FREQUENCY
In the application circuit, the 350 kHz operation is
selected by leaving RT and SYNC open. Connecting
a 180 kΩ to 68 kΩ resistor between RT (pin 28) and
analog ground can be used to set the switching
frequency to 280 kHz to 700 kHz. To calculate the
RT resistor, use the equation below:
500 kHz
R
+
100 [kW]
Switching Frequency
(1)
OUTPUT FILTER
The output filter is composed of a 4.7-µH inductor
and two 470-µF capacitors. The inductor is a low dc
resistance (12 mΩ) type, Coiltronics UP3B-4R7. The
capacitors used are 4-V POSCAP types with a
maximum ESR of 0.040
Ω.
The feedback loop is
compensated so that the unity gain frequency is
approximately 25 kHz.
PCB LAYOUT
shows a generalized PCB layout guide for
the TPS54610.
The VIN pins are connected together on the
printed-circuit board (PCB) and bypassed with a
low-ESR ceramic-bypass capacitor. Care should be
taken to minimize the loop area formed by the
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