TPS54310
SLVS412A – DECEMBER 2001 – REVISED JUNE 2002
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TJ
–40°C to 125°C
OUTPUT VOLTAGE
0.9 V to 3.3 V
PACKAGED DEVICES
PLASTIC HTSSOP
(PWP)(1)
TPS54310PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54310PWPR). See application section of
data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54310
VIN, SS/ENA, SYNC
RT
Input voltage range VI
range,
VSENSE
BOOT
VBIAS, PWRGD, COMP
Output voltage range VO
range,
Source current IO
current,
PH
PH
COMP, VBIAS
PH
Sink current
Voltage differential
Continuous power dissipation
Operating virtual junction temperature range, TJ
Storage temperature, Tstg
COMP
SS/ENA,PWRGD
AGND to PGND
–0.3 to 7
–0.3 to 6
–0.3 to 4
–0.3 to 17
–0.3 to 7
–0.6 to 10
Internally Limited
6
6
6
10
±0.3
mA
A
mA
mA
V
UNIT
V
V
V
V
V
V
See Power Dissipation
Rating Table
–40 to 150
–65 to 150
°C
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300
°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage range, VI
Operating junction temperature, TJ
3
–40
NOM
MAX
6
125
UNIT
V
°C
PACKAGE DISSIPATION RATINGS
(1) (2)
PACKAGE
20-Pin PWP with solder
20-Pin PWP without solder
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
26.0°C/W
57.5°C/W
TA
=
25°C
POWER RATING
3.85 W(3)
1.73 W
TA = 70°C
POWER RATING
2.12 W
0.96 W
TA = 85°C
POWER RATING
1.54 W
0.69 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3”
×
3”, 2 layers, Thickness: 0.062”
2. 1.5 oz copper traces located on the top of the PCB
3. 1.5 oz copper ground plane on the bottom of the PCB
4. Ten thermal vias (see recommended land pattern in application section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
2
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