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TPS51117RGYR 参数 Datasheet PDF下载

TPS51117RGYR图片预览
型号: TPS51117RGYR
PDF下载: 下载PDF文件 查看货源
内容描述: 单同步降压控制器 [SINGLE SYNCHRONOUS STEP-DOWN CONTROLLER]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器
文件页数/大小: 31 页 / 1285 K
品牌: TI [ TEXAS INSTRUMENTS ]
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TPS51117  
www.ti.com...................................................................................................................................... SLVS631B DECEMBER 2005REVISED SEPTEMBER 2009  
APPLICATION INFORMATION  
LOOP COMPENSATION AND EXTERNAL PARTS SELECTION  
D-CAP™ Mode Operation  
A buck converter system using D-CAP™ Mode can be simplified as shown in Figure 23.  
VIN  
R1  
DRVH  
Lx  
PWM  
VFB  
Control  
Logic  
and  
-
I
Ic  
+
L
Driver  
Io  
DRVL  
+
R2  
0.75V  
ESR  
Co  
Vc  
RL  
Voltage Divider  
Switching Modulator  
Output Capacitor  
Figure 23. Simplified Diagram of the Modulator  
The VFB voltage is compared with the internal reference voltage after the divider resistors. The PWM comparator  
determines the timing to turn on the top MOSFET. The gain and speed of the comparator is high enough to keep  
the voltage at the beginning of each on cycle (or the end of off cycle) substantially constant. The DC output  
voltage may have line regulation due to ripple amplitude that slightly increases as the input voltage increases.  
For loop stability, the 0 dB frequency, f , defined in the follow equation must be lower than 1/4 of the switching  
0
frequency.  
ƒ
sw  
4
1
ƒ +  
v
o
2p   ESR   Co  
(6)  
As f is determined solely by the output capacitor characteristics, loop stability of D-CAP™ Mode is determined  
0
by capacitor chemistry. For example, specialty polymer capacitors (SP-CAP) have Co in the order of several 100  
μF and ESR in range of 10 m. These values make f in the order of 100 kHz or less and the loop is stable.  
0
However, ceramic capacitors have f0 at more than 700 kHz, which is not suitable for this operational mode.  
Although D-CAP™ Mode provides many advantages such as ease-of-use, minimum external component  
configuration, and extremely short response time, due to not employing an error amplifier in the loop, a sufficient  
feedback signal needs to be provided by an external circuit to reduce the jitter level. The required signal level is  
approximately 15 mV at the comparing point. This generates Vripple = (VOUT/0.75) × 15 mV at the output node.  
The output capacitor ESR should meet this requirement.  
The external component selection is simple in D-CAP™ Mode:  
1. Determine the value of R1 and R2  
The recommended R2 value is 10 kto 100 k. Calculate R1 by Equation 7.  
ǒVOUT * 0.75Ǔ  
R1 +  
  R2  
0.75  
(7)  
17  
2. Choose RTON  
Copyright © 2005–2009, Texas Instruments Incorporated  
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Product Folder Link(s) :TPS51117