TPS3823-33DBVR 参数 Datasheet PDF下载

TPS3820 xx, TPS3823 xx, TPS3824 xx, TPS3825 xx, TPS3828 xx

PROCESSOR SUPERVISORY CIRCUITS

SLVS165E – APRIL 1998 – REVISED DECEMBER 2002

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted) (continued)

PARAMETER

IIH(AV)

IIL(AV)

Average high-level input current

WDI

Average low-level input current

WDI

IIH

High-level input current

MR

WDI

IIL

Low-level inp t c rrent

Lo le el input current

MR

TPS382x-25

IOS

Output short-circuit current

Out ut short circuit

(see Note 4)

TPS382x-30

RESET

TPS382x-33

TPS382x-50

IDD

Supply current

Internal pullup resistor at MR

Ci

Input capacitance at MR, WDI

WDI and MR unconnected,

Outputs unconnected

15

52

VDD = VIT, max + 0.2 V,

VO = 0 V

–400

400

–800

25

µA

kΩ

pF

A

µA

TEST CONDITIONS

WDI = VDD,

time average (dc = 88%)

WDI = 0.3 V, VDD = 5.5 V

time average (dc = 12%)

WDI = VDD

MR = VDD

×

0.7,

VDD = 5.5 V

WDI = 0.3 V, VDD = 5.5 V

MR = 0.3 V, VDD = 5.5 V

MIN

TYP

120

–15

140

–40

140

–110

190

–60

190

–160

µA

MAX

UNIT

VI = 0 V to 5.5 V

5

NOTE 4: The RESET short-circuit current is the maximum pullup current when RESET is driven low by a

µP

bidirectional reset pin.

timing requirements at R

L

= 1 MΩ, C

L

= 50 pF, T

A

= 25°C

PARAMETER

at VDD

tw

Pulse width

at MR

at WDI

VDD = VIT– + 0.2 V,

VDD

≥

VIT– + 0.2 V,

VDD

≥

VIT– + 0.2 V,

TEST CONDITIONS

VDD = VIT- - 0.2 V

VIL = 0.3 x VDD,

VIL = 0.3 x VDD,

VIH = 0.7 x VDD

VIH = 0.7 x VDD

MIN

6

1

100

MAX

UNIT

µs

µs

ns

switching characteristics at R

L

= 1 MΩ, C

L

= 50 pF, T

A

= 25°C

PARAMETER

TPS3820

ttout

td

Watchdog time out

Delay

Dela time

TPS3823/4/8

TPS3820

TPS3823/4/5/8

MR to RESET delay

(TPS3820/3/5/8)

VDD to RESET delay

MR to RESET delay (TPS3824/5)

TEST CONDITIONS

VDD

≥

VIT– + 0.2 V,

See Timing Diagram

VDD

≥V

IT– +0.2 V,

See timing diagram

VDD

≥V

IT– +0.2 V,

VIL=0.3 x VDD,

VIH=0.7 x VDD

VIL = VIT- - 0.2 V,

VIH = VIT- + 0.2 V

VDD

≥V

IT– +0.2 V,

VIL=0.3 x VDD,

VIH=0.7 x VDD

VIL = VIT- - 0.2 V,

VIH = VIT- + 0.2 V

MIN

112

0.9

15

120

TYP

200

1.6

25

200

MAX

310

2.5

37

300

0.1

µs

25

ms

UNIT

ms

s

tPHL

Propagation (delay) time,

high-to-low-level

high to low level output

tPLH

Propagation (delay) time,

low-to-high-level

low to high level output

0.1

µs

25

VDD to RESET delay (TPS3824/5)

6

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