TPS3809J25 Q1, TPS3809L30 Q1, TPS3809K33 Q1, TPS3809I50 Q1
3 PIN SUPPLY VOLTAGE SUPERVISORS
SGLS142 – DECEMBER 2002
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VDD = 2.5 V to 6 V, IOH = –500
µA
VDD = 3.3 V,
IOH = –2 mA
TA = –40°C to 25°C
VDD = 6 V IOH = –4 mA
V,
4
TA = 125°C
VDD = 2 V to 6 V,
VDD = 3.3 V,
VDD = 6 V,
VDD
≥
1.1 V,
IOL = 500
µA
IOL = 2 mA
IOL = 4 mA
IOL = 50
µA
2.20
TA = –40°C to 125 C
40 C 125°C
TA = –40°C to 85°C
TA = –40°C to 125°C
2.58
2.87
4.45
4.4
2.25
2.64
2.93
4.55
4.55
30
35
40
60
VDD = 2 V, Output unconnected
VDD = 6 V, Output unconnected
9
20
15
30
µA
A
mV
MIN
VDD–0.2
VDD–0.4
VDD–0.4
VDD–0.5
0.2
0.4
0.4
0.2
2.30
2.70
2.99
4.65
4.65
V
V
V
TYP
MAX
UNIT
VOH
High-level o tp t oltage
High le el output voltage
V
VOL
Low level output
Low-level out ut voltage
Power-up reset voltage (see Note 2)
TPS3809J25
Negative-going input
threshold voltage
(see Note 3)
TPS3809L30
TPS3809K33
TPS3809I50
TPS3809J25
TPS3809L30
VIT–
Vhys
Hysteresis
H steresis
TPS3809K33
TPS3809I50
IDD
Ci
Supply current
S ppl c rrent
Input capacitance
VI = 0 V to VDD
5
pF
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD
≥
15
µs/V.
3. To ensure best stability of the threshold voltage, a bypass capacitor ( 0.1
µF
ceramic) should be placed near the supply terminals.
timing requirements at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER
tw
Pulse width
at VDD
VDD = VIT– + 0.2 V,
TEST CONDITIONS
VDD = VIT– – 0.2 V
MIN
3
TYP
MAX
UNIT
µs
switching characteristics at R
L
= 1 MΩ, C
L
= 50 pF, T
A
= 25°C
PARAMETER
td
tPHL
Delay time
Propagation (delay) time, high-to-low-level output
VDD to RESET delay
TEST CONDITIONS
VDD
≥
VIT– + 0.2 V,
See timing diagram
VIL = VIT– –0.2 V,
VIH = VIT– +0.2 V
MIN
120
TYP
200
1
MAX
280
UNIT
ms
µs
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TI [ TEXAS INSTRUMENTS ]
