SBVS050I – MAY 2004 – REVISED AUGUST 2008...........................................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAMS
V
DD
V
DD
90k
RESET
MR
Reset
Logic
Timer
SENSE
−
+
V
DD
V
DD
90k
MR
SENSE
R
1
−
TPS3808G01
Adjustable Voltage
RESET
Reset
Logic
Timer
C
T
0.4V
V
REF
C
T
R
2
0.4V
V
REF
+
R
1
+ R
2
= 4MΩ
GND
GND
Adjustable Voltage Version
Fixed Voltage Version
Figure 1. Adjustable and Fixed Voltage Versions
PIN ASSIGNMENTS
DBV PACKAGE
SOT23
(TOP VIEW)
DRV PACKAGE
2mm × 2mm QFN
(TOP VIEW)
V
DD
SENSE
C
T
1
2
3
Power
PAD
6
5
4
RESET
GND
MR
RESET
GND
MR
1
2
3
6
5
4
V
DD
SENSE
C
T
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
RESET
SOT23 (DBV)
PIN NO.
1
DESCRIPTION
RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either the
SENSE input is lower than the threshold voltage (V
IT
) or the MR pin is set to a logic low). RESET will remain
low (asserted) for the reset period after both SENSE is above V
IT
and MR is set to a logic high. A pull-up
resistor from 10kΩ to 1MΩ should be used on this pin, and allows the reset pin to attain voltages higher than
V
DD
.
Ground
Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to V
DD
by a 90kΩ pull-up
resistor.
Reset period programming pin. Connecting this pin to V
DD
through a 40kΩ to 200kΩ resistor or leaving it
open results in fixed delay times (see
Connecting this pin to a ground referenced
capacitor
≥
100pF gives a user-programmable delay time. See the
section
for more information.
This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold
voltage V
IT
, then RESET is asserted.
Supply voltage. It is good analog design practice to place a 0.1µF ceramic capacitor close to this pin.
PowerPAD. Connect to ground plane to enhance thermal performance of package.
GND
MR
C
T
2
3
4
SENSE
V
DD
PowerPAD
5
6
4
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