TPS31xxExx, TPS31xxH20, TPS31xxK33
ULTRALOW SUPPLY CURRENT/SUPPLY VOLTAGE SUPERVISORY CIRCUITS
SLVS363B − AUGUST 2001 − REVISED SEPTEMBER 2004
www.ti.com
TIMING REQUIREMENTS AT R
L
= 1 MΩ, C
L
= 50 PF, T
A
= −40°C TO 85°C
PARAMETER
tt(out) Time-out period
at WDI
at VDD
at MR
tw
Pulse width
at SENSE
at PFI
at WDI
TEST CONDITIONS
VDD
≥
0.85 V
VIH = 1.1
×
VIT, VIL = 0.9
×
VIT−, VIT− = 0.86 V
VDD
≥
VIT + 0.2 V, VIL = 0.3
×
VDD, VIH = 0.7
×
VDD
VDD
≥
VIT,
VIH = 1.1
×
VIT−(S), VIL = 0.9
×
VIT−(S)
VDD
≥
0.85 V,
VIH = 1.1
×
VIT−(S),VIL = 0.9
×
VIT−(S)
VDD
≥
VIT,
VIL = 0.3
×
VDD,
VIH = 0.7
×
VDD
MIN
0.55
20
0.1
20
20
0.3
µs
TYP
1.1
MAX
1.65
UNIT
s
SWITCHING CHARACTERISTICS AT R
L
= 1 MΩ, C
L
= 50 PF, T
A
= −40°C TO 85°C
PARAMETER
td
tPHL
tPLH
tPHL
Delay time
VDD to RESET or
RSTVDD delay
VDD to RESET or
RSTVDD delay
SENSE to RESET or
RSTSENSE delay
SENSE to RESET or
RSTSENSE delay
TEST CONDITIONS
VDD
≥
1.1
×
VIT,
MR = 0.7
×
VDD,
See timing diagram
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
0.8 V,
VIH = 1.1
×
VIT,
VIL = 0.9
×
VIT
VDD
≥
1.1
×
VIT,
VIL = 0.3
×
VDD,
VIH = 0.7
×
VDD
MIN
65
TYP
130
MAX
195
UNIT
ms
Propagation delay time, high-to-low level output
Propagation delay time, low-to-high level output
40
µs
40
µs
Propagation delay time, high-to-low level output
40
tPLH
Propagation delay time, high-to-low level output
40
µs
tPHL
Propagation delay time, high-to-low level output
PFI to PFO delay
40
µs
tPLH
Propagation delay time, low-to-high level output
PFI to PFO delay
MR to RESET.
RSTVDD,
RSTSENSE delay
MR to RESET.
RSTVDD,
RSTSENSE delay
300
µs
tPHL
Propagation delay time, low-to-high level output
1
5
µs
s
tPLH
Propagation delay time, low-to-high level output
12
TI [ TEXAS INSTRUMENTS ]
