TPS3103xxx
TPS3106xxx
TPS3110xxx
SLVS363E – AUGUST 2001 – REVISED SEPTEMBER 2007
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
MR
I
IL
Low-level input current
High-level output current
at RESET
(2)
SENSE, PFI,
WDI
Open-drain
TEST CONDITIONS
MR = 0 V, V
DD
= 3.3 V
SENSE, PFI, WDI = 0 V,
V
DD
= 3.3 V
V
DD
= V
IT
+ 0.2 V, V
OH
= 3.3 V
V
DD
> V
IT
(average current),
V
DD
< 1.8 V
I
DD
Supply current
V
DD
> V
IT
(average current),
V
DD
> 1.8 V
V
DD
< V
IT
, V
DD
< 1.8 V
V
DD
< V
IT
, V
DD
> 1.8 V
Internal pull-up resistor at MR
C
I
(2)
Input capacitance at MR, SENSE, PFI, WDI V
I
= 0 V to V
DD
Also refers to RSTVDD and RSTSENSE.
70
100
1
1.2
2
MIN
–47
–25
TYP
–33
MAX
–25
25
200
3
4.5
22
27
130
kΩ
pF
μA
UNIT
μA
nA
nA
I
OH
SWITCHING CHARACTERISTICS
At R
L
= 1 MΩ, C
L
= 50 pF, and T
A
= –40°C to +85°C, unless otherwise noted.
PARAMETER
t
D
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
Delay time
Propagation delay time,
high-to-low level output
Propagation delay time,
low-to-high level output
Propagation delay time,
high-to-low level output
Propagation delay time,
high-to-low level output
Propagation delay time,
high-to-low level output
Propagation delay time,
low-to-high level output
Propagation delay time,
low-to-high level output
Propagation delay time,
low-to-high level output
V
DD
to RESET or
RSTVDD delay
V
DD
to RESET or
RSTVDD delay
SENSE to RESET or
RSTSENSE delay
SENSE to RESET or
RSTSENSE delay
PFI to PFO delay
PFI to PFO delay
MR to RESET.
RSTVDD,
RSTSENSE delay
MR to RESET.
RSTVDD,
RSTSENSE delay
TEST CONDITIONS
V
DD
≥
1.1
×
V
IT
, MR = 0.7
×
V
DD
, See
Timing Diagrams
V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
V
DD
≥
0.8 V, V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT
V
DD
≥
1.1
×
V
IT
, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
1
MIN
65
TYP
130
MAX
195
40
40
40
40
40
300
UNIT
ms
μs
μs
μs
μs
μs
μs
5
μs
t
PLH
V
DD
≥
1.1
×
V
IT
, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
1
5
μs
TIMING REQUIREMENTS
At R
L
= 1 MΩ, C
L
= 50 pF, and T
A
= –40°C to +85°C, unless otherwise noted.
PARAMETER
t
T(OUT)
Time-out period
at WDI
at V
DD
at MR
t
W
Pulse width
at SENSE
at PFI
at WDI
V
DD
≥
0.85 V
V
IH
= 1.1
×
V
IT
, V
IL
= 0.9
×
V
IT–
, V
IT–
= 0.86 V
V
DD
≥
V
IT
+ 0.2 V, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
V
DD
≥
V
IT
, V
IH
= 1.1
×
V
IT
−
(S)
, V
IL
= 0.9
×
V
IT
−
(S)
V
DD
≥
0.85 V, V
IH
= 1.1
×
V
IT
−
(S)
,V
IL
= 0.9
×
V
IT
−
(S)
V
DD
≥
V
IT
, V
IL
= 0.3
×
V
DD
, V
IH
= 0.7
×
V
DD
TEST CONDITIONS
MIN
0.55
20
0.1
20
20
0.3
μs
TYP
1.1
MAX
1.65
UNIT
s
4
Copyright © 2001–2007, Texas Instruments Incorporated
TI [ TEXAS INSTRUMENTS ]
