欢迎访问ic37.com |
会员登录 免费注册
发布采购

TPS23750PWPR 参数 Datasheet PDF下载

TPS23750PWPR图片预览
型号: TPS23750PWPR
PDF下载: 下载PDF文件 查看货源
内容描述: 结合100 -V型IEEE 802.3af PD和DC / DC控制器 [INTEGRATED 100-V IEEE 802.3af PD AND DC/DC CONTROLLER]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管PC
文件页数/大小: 38 页 / 2852 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号TPS23750PWPR的Datasheet PDF文件第6页浏览型号TPS23750PWPR的Datasheet PDF文件第7页浏览型号TPS23750PWPR的Datasheet PDF文件第8页浏览型号TPS23750PWPR的Datasheet PDF文件第9页浏览型号TPS23750PWPR的Datasheet PDF文件第11页浏览型号TPS23750PWPR的Datasheet PDF文件第12页浏览型号TPS23750PWPR的Datasheet PDF文件第13页浏览型号TPS23750PWPR的Datasheet PDF文件第14页  
TPS23750  
TPS23770  
www.ti.com  
SLVS590AJULY 2005REVISED AUGUST 2005  
The COMP output should not be over-driven when the internal error amplifier is active. The amplifier can source  
and sink significant currents which will greatly increase power dissipation. TMR may be pulled low to turn the  
converter off when the internal error amplifier is used. The error amplifier will source current when COMP is  
pulled below its saturated low voltage due to the nature of the class AB amplifier stage.  
DET – Connect a 24.9 k, ±1% resistor (RDET), between DET and VDD. RDET is connected across the input line  
when VDD lies between 1.4 V and 10.1 V, and is disconnected when the line voltage exceeds 12 V to conserve  
power. RDET may be adjusted to compensate for input diode characteristics.  
FB – This is the internal dc/dc converter error amplifier’s inverting input. FB is used for output voltage feedback  
and loop compensation. FB equals 1.5 V when the feedback loop is in regulation. FB should be tied to RTN  
when the error amplifier is disabled using MODE. The internal level translator drives this pin with a source  
impedance of about 15 kwhen it is enabled using SEN.  
FREQ – A resistor connected from FREQ to RTN programs the converter switching frequency. This feature  
allows an existing design to be easily upgraded to use the TPS23750 without requiring redesign of the magnetics  
and filtering. While the oscillator is characterized between 100 kHz and 500 kHz, it operates properly down to a  
frequency of a few kilohertz.  
15000  
R
(kW) +  
FREQ  
Switching_Frequency (kHz)  
(1)  
Although this expression is reasonably accurate, the frequency will be slightly lower than predicted at higher  
frequencies.  
FREQ must not be shorted to ground or have voltage applied.  
GATE – DC/DC converter’s switching MOSFET driver output. This pin has an internal pull-down to keep the  
external switching MOSFET off when the converter is inactive.  
MODE –This pin disables the converter error amplifier, allowing an optocoupler to drive the PWM comparator  
directly from COMP. Connecting MODE to RTN enables the error amplifier, and to VBIAS disables it. MODE  
should not be left floating.  
RSN – This pin is the current-mode controller’s quiet "ground" reference for current sensing and other low-level  
signals. RTN, RSN, and COM should be tied together.  
RSP – This pin is the current-mode controller’s current-sense input. Current-mode control monitors the switching  
MOSFET peak current, which is sensed as voltage between RSP and RSN, to set the PWM duty cycle. The  
peak current limit is established by limiting the maximum sense voltage to about 0.5 V.  
MOSFET current may rise to high levels during the blanking period when there is a short in the power circuit. If  
the RSP peak voltage exceeds 0.75 V on four successive switching cycles, the converter is turned off and a  
hiccup cycle is started.  
If the blanking is sufficient to eliminate the need for an input RC filter, this pin may be directly connected to the  
sense resistor.  
RTN – An internal MOSFET connects this pin to VSS. This MOSFET is controlled by the PoE section UVLO,  
inrush limit, current limit, thermal limit, and fault voltage limiting.  
Most applications connect RSN, COM, and RTN together through a ground plane.  
SEN – SEN is the negative input for the level translator. It can be used in buck converters as demonstrated in  
Figure 40. The translator is enabled by connecting SEN above 1 V with respect to VSS. The level translator  
applies VSENP-SEN to the FB pin through an internal 15 kresistor. This feature simplifies feedback voltage  
sensing above RTN. Connect SEN to RSN if the level translator is not used.  
SENP – SENP is the positive input for the level translator. It is used in conjunction with SEN as demonstrated in  
Figure 40. The presence of this pin allows a filter inductor to be placed in the positive power rail between VDD  
and the output. Connect SENP to VDD when the level translator is disabled. The voltage on SENP should always  
be greater than the voltage on SEN.  
TMR – Connect a capacitor from TMR to RTN to program the softstart and hiccup timer functions. Pull this pin to  
RTN to disable the converter.  
10  
 复制成功!