SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
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6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the ePWM, software trigger, or
from an external ADCSOC signal. If the SMODE bit is 1, the ADC will do conversions on two selected
channels on every Sample/Hold pulse. The conversion time and latency of the result register update are
explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register
update. The selected channels will be sampled simultaneously at the falling edge of the Sample/Hold
pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum) or 16 ADC
clocks wide (maximum).
NOTE
In simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
Sample n
Analog Input on
Channel Ax
Analog Input on
Channel Bx
ADC Clock
Sample and Hold
SH Pulse
SMODE Bit
t
d(SH)
ADC Event Trigger from
ePWM or Other Sources
t
SH
Sample n+1
Sample n+2
t
dschA0_n+1
t
dschA0_n
t
dschB0_n
t
dschB0_n+1
Figure 6-27. Simultaneous Sampling Mode Timing
Table 6-42. Simultaneous Sampling Mode Timing
SAMPLE n
t
d(SH)
t
SH
t
d(schA0_n)
t
d(schB0_n )
t
d(schA0_n+1)
t
d(schB0_n+1 )
Delay time from event trigger to
sampling
Sample/Hold width/Acquisition
Width
Delay time for first result to
appear in Result register
Delay time for first result to
appear in Result register
Delay time for successive results
to appear in Result register
Delay time for successive results
to appear in Result register
2.5t
c(ADCCLK)
(1 + Acqps) *
t
c(ADCCLK)
4t
c(ADCCLK)
5t
c(ADCCLK)
(3 + Acqps) * t
c(ADCCLK)
(3 + Acqps) * t
c(ADCCLK)
80 ns with
Acqps = 0
320 ns
400 ns
240 ns
240 ns
Acqps value = 0–15
ADCTRL1[8:11]
SAMPLE n + 1
AT 12.5 MHz
ADC CLOCK,
t
c(ADCCLK)
= 80 ns
REMARKS
130
Electrical Specifications
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