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SPRS230M – OCTOBER 2003 – REVISED MARCH 2011
Table 6-37. SPI Slave Mode External Timing (Clock Phase = 1)
(1)
NO.
12
13
14
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
su(SOMI-SPCH)S
17
t
su(SOMI-SPCL)S
t
v(SPCL-SOMI)S
18
t
v(SPCH-SOMI)S
t
su(SIMO-SPCH)S
t
su(SIMO-SPCL)S
t
v(SPCH-SIMO)S
22
t
v(SPCL-SIMO)S
Cycle time, SPICLK
Pulse duration, SPICLK high (clock polarity = 0)
Pulse duration, SPICLK low (clock polarity = 1)
Pulse duration, SPICLK low (clock polarity = 0)
Pulse duration, SPICLK high (clock polarity = 1)
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
(2) (3) (4)
MIN
8t
c(LCO)
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.125t
c(SPC)S
0.125t
c(SPC)S
0.75t
c(SPC)S
0.75t
c(SPC) S
35
35
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
MAX
0.5t
c(SPC)S
0.5t
c(SPC) S
0.5t
c(SPC) S
0.5t
c(SPC)S
UNIT
ns
ns
ns
ns
ns
21
ns
ns
(1)
(2)
(3)
(4)
The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
c(SPC)
= SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)
Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate:
Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX
Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
12
SPICLK
(clock polarity = 0)
13
14
SPICLK
(clock polarity = 1)
17
18
SPISOMI
SPISOMI Data Is Valid
21
22
SPISIMO
SPISIMO Data
Must Be Valid
Data Valid
SPISTE
(A)
A.
In the slave mode, the SPISTE signal should be asserted low at least 0.5t
c(SPC)
before the valid SPI clock edge and
remain low for at least 0.5t
c(SPC)
after the receiving edge (SPICLK) of the last data bit.
Figure 6-23. SPI Slave Mode External Timing (Clock Phase = 1)
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Electrical Specifications
125
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