TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
3.6.2 Watchdog Block
The watchdog block on the 2833x/2823x device is similar to the one used on the 240x and 281x devices.
The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the
8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter
or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will
reset the watchdog counter. Figure 3-13 shows the various functional blocks within the watchdog module.
WDCR (WDPS[2:0])
WDCR (WDDIS)
WDCNTR[7:0]
OSCCLK
WDCLK
Watchdog
Prescaler
8-Bit
Watchdog
Counter
CLR
/512
Clear Counter
Internal
Pullup
WDKEY[7:0]
WDRST
WDINT
Generate
Output Pulse
(512 OSCCLKs)
Watchdog
55 + AA
Key Detector
Good Key
XRS
Bad
WDCHK
Key
Core-reset
SCSR (WDENINT)
WDCR (WDCHK[2:0])
1
0
1
WDRST(A)
A. The WDRST signal is driven low for 512 OSCCLK cycles.
Figure 3-13. Watchdog Module
The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.
In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains
functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the
LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7, Low-Power
Modes Block, for more details.
In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of
IDLE mode.
In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so
is the WATCHDOG.
Copyright © 2007–2011, Texas Instruments Incorporated
Functional Overview
63
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