TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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3.6 System Control
This section describes the oscillator, PLL and clocking mechanisms, the watchdog function and the low
power modes. Figure 3-8 shows the various clock and reset domains that will be discussed.
C28x Core
SYSCLKOUT
CLKIN
System
Control
Register
Clock Enables
LSPCLK
LOSPCP
Bridge
I/O
Peripheral
Registers
SPI-A, SCI-A/B/C
Clock Enables
I2C-A
Clock Enables
/2
Bridge
Bridge
Bridge
I/O
I/O
I/O
Peripheral
Registers
eCAN-A/B
GPIO
Mux
Clock Enables
Peripheral
Registers
ePWM1/../6, HRPWM1/../6,
eCAP1/../6, eQEP1/2
Clock Enables
LSPCLK
LOSPCP
Peripheral
Registers
McBSP-A/B
Clock Enables
HSPCLK
HISPCP
16 Channels
ADC
Registers
12-Bit ADC
Result
Registers
DMA
Clock Enables
A. CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency
as SYSCLKOUT). See Figure 3-9 for an illustration of how CLKIN is derived.
Figure 3-8. Clock and Reset Domains
NOTE
There is a 2-SYSCLKOUT cycle delay from when the write to PCLKCR0/1/2 registers
(enables peripheral clocks) occurs to when the action is valid. This delay must be taken into
account before attempting to access the peripheral configuration registers.
58
Functional Overview
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