TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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Contents
1
2
3
TMS320F2833x, TMS320F2823x DSCs .................................................................................. 11
1.1
Features .................................................................................................................... 11
Getting Started ............................................................................................................. 12
1.2
Introduction ...................................................................................................................... 13
2.1
Pin Assignments ........................................................................................................... 15
Signal Descriptions ........................................................................................................ 24
2.2
Functional Overview .......................................................................................................... 34
3.1
Memory Maps .............................................................................................................. 35
Brief Descriptions .......................................................................................................... 42
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
C28x CPU ....................................................................................................... 42
Memory Bus (Harvard Bus Architecture) .................................................................... 42
Peripheral Bus .................................................................................................. 42
Real-Time JTAG and Analysis ................................................................................ 43
External Interface (XINTF) .................................................................................... 43
Flash ............................................................................................................. 43
M0, M1 SARAMs ............................................................................................... 43
3.2.8
3.2.9
L0, L1, L2, L3, L4, L5, L6, L7 SARAMs ..................................................................... 44
Boot ROM ........................................................................................................ 44
3.2.9.1 Peripheral Pins Used by the Bootloader ........................................................ 45
3.2.10 Security .......................................................................................................... 45
3.2.11 Peripheral Interrupt Expansion (PIE) Block ................................................................. 47
3.2.12 External Interrupts (XINT1–XINT7, XNMI) .................................................................. 47
3.2.13 Oscillator and PLL .............................................................................................. 47
3.2.14 Watchdog ........................................................................................................ 47
3.2.15 Peripheral Clocking ............................................................................................. 47
3.2.16 Low-Power Modes .............................................................................................. 47
3.2.17 Peripheral Frames 0, 1, 2, 3 (PFn) ........................................................................... 48
3.2.18 General-Purpose Input/Output (GPIO) Multiplexer ......................................................... 48
3.2.19 32-Bit CPU-Timers (0, 1, 2) ................................................................................... 48
3.2.20 Control Peripherals ............................................................................................. 49
3.2.21 Serial Port Peripherals ......................................................................................... 49
Register Map ............................................................................................................... 50
3.3
3.4
3.5
Device Emulation Registers .............................................................................................. 52
Interrupts .................................................................................................................... 53
3.5.1
External Interrupts .............................................................................................. 57
3.6
System Control ............................................................................................................ 58
3.6.1
OSC and PLL Block ............................................................................................ 59
3.6.1.1 External Reference Oscillator Clock Option .................................................... 60
3.6.1.2 PLL-Based Clock Module ......................................................................... 61
3.6.1.3 Loss of Input Clock ................................................................................ 62
Watchdog Block ................................................................................................. 63
3.6.2
3.7
Low-Power Modes Block ................................................................................................. 64
4
Peripherals ....................................................................................................................... 65
4.1
DMA Overview ............................................................................................................. 65
32-Bit CPU-Timers 0/1/2 ................................................................................................. 67
4.2
2
Contents
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