TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439I–JUNE 2007–REVISED MARCH 2011
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXINT3SEL
GPIOLMPSEL
LPMCR0
GPIOXINT7SEL
GPIOXNMISEL
Low-Power
Modes Block
External Interrupt
MUX
PIE
GPxDAT (read)
Asynchronous
path
GPxQSEL1/2
GPxCTRL
GPxPUD
00
01
N/C
Peripheral 1 Input
Input
Qualification
Internal
Pullup
Peripheral 2 Input
Peripheral 3 Input
10
11
Asynchronous path
GPxTOGGLE
GPxCLEAR
GPxSET
GPIOx pin
00
01
10
11
GPxDAT (latch)
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
High-Impedance
Output Control
00
01
GPxDIR (latch)
Peripheral 1 Output Enable
0 = Input, 1 = Output
XRS
Peripheral 2 Output Enable
Peripheral 3 Output Enable
10
11
= Default at Reset
GPxMUX1/2
A. x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
B. GPxDAT latch/read are accessed at the same memory location.
C. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the
TMS320x2833x, 2823x System Control and Interrupts Reference Guide (literature number SPRUFB0 ) for pin-specific
variations.
Figure 4-18. GPIO MUX Block Diagram
Copyright © 2007–2011, Texas Instruments Incorporated
Peripherals
101
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