TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
SPRS439I–JUNE 2007–REVISED MARCH 2011
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Table 4-12. SCI-C Registers(1) (2)
NAME
ADDRESS
0x7770
0x7771
0x7772
0x7773
0x7774
0x7775
0x7776
0x7777
0x7779
0x777A
0x777B
0x777C
0x777F
SIZE (x16)
DESCRIPTION
SCI-C Communications Control Register
SCI-C Control Register 1
SCICCRC
1
1
1
1
1
1
1
1
1
1
1
1
1
SCICTL1C
SCIHBAUDC
SCILBAUDC
SCICTL2C
SCIRXSTC
SCIRXEMUC
SCIRXBUFC
SCITXBUFC
SCIFFTXC(2)
SCIFFRXC(2)
SCIFFCTC(2)
SCIPRC
SCI-C Baud Register, High Bits
SCI-C Baud Register, Low Bits
SCI-C Control Register 2
SCI-C Receive Status Register
SCI-C Receive Emulation Data Buffer Register
SCI-C Receive Data Buffer Register
SCI-C Transmit Data Buffer Register
SCI-C FIFO Transmit Register
SCI-C FIFO Receive Register
SCI-C FIFO Control Register
SCI-C Priority Control Register
(1) Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2) These registers are new registers for the FIFO mode.
94
Peripherals
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