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SPRS439I – JUNE 2007 – REVISED MARCH 2011
4.2
32-Bit CPU-Timers 0/1/2
There are three 32-bit CPU-timers on the devices (CPU-TIMER0/1/2).
Timer 2 is reserved for DSP/BIOS™. CPU-Timer 0 and CPU-Timer 1 can be used in user applications.
These timers are different from the timers that are present in the ePWM modules.
NOTE
NOTE: If the application is not using DSP/BIOS, then CPU-Timer 2 can be used in the
application.
Reset
Timer Reload
16-Bit Timer Divide-Down
TDDRH:TDDR
32-Bit Timer Period
PRDH:PRD
SYSCLKOUT
TCR.4
(Timer Start Status)
16-Bit Prescale Counter
PSCH:PSC
Borrow
32-Bit Counter
TIMH:TIM
Borrow
TINT
Figure 4-2. CPU-Timers
The timer interrupt signals (TINT0, TINT1, TINT2) are connected as shown in
INT1
to
INT12
PIE
TINT0
CPU-TIMER 0
28x
CPU
TINT1
INT13
XINT13
INT14
TINT2
CPU-TIMER 2
(Reserved for DSP/BIOS)
CPU-TIMER 1
A.
B.
The timer registers are connected to the memory bus of the C28x processor.
The timing of the timers is synchronized to SYSCLKOUT of the processor clock.
Figure 4-3. CPU-Timer Interrupt Signals and Output Signal
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Peripherals
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