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SPRS439I – JUNE 2007 – REVISED MARCH 2011
The PLL, clocking, watchdog and low-power modes, are controlled by the registers listed in
Table 3-16. PLL, Clocking, Watchdog, and Low-Power Mode Registers
NAME
PLLSTS
Reserved
HISPCP
LOSPCP
PCLKCR0
PCLKCR1
LPMCR0
Reserved
PCLKCR3
PLLCR
SCSR
WDCNTR
Reserved
WDKEY
Reserved
WDCR
Reserved
MAPCNF
ADDRESS
0x00 7011
0x00 7012 – 0x00 7018
0x00 701A
0x00 701B
0x00 701C
0x00 701D
0x00 701E
0x00 701F
0x00 7020
0x00 7021
0x00 7022
0x00 7023
0x00 7024
0x00 7025
0x00 7026 – 0x00 7028
0x00 7029
0x00 702A – 0x00 702D
0x00 702E
SIZE (x16)
1
7
1
1
1
1
1
1
1
1
1
1
1
1
3
1
4
1
PLL Status Register
Reserved
High-Speed Peripheral Clock Pre-Scaler Register
Low-Speed Peripheral Clock Pre-Scaler Register
Peripheral Clock Control Register 0
Peripheral Clock Control Register 1
Low Power Mode Control Register 0
Reserved
Peripheral Clock Control Register 3
PLL Control Register
System Control and Status Register
Watchdog Counter Register
Reserved
Watchdog Reset Key Register
Reserved
Watchdog Control Register
Reserved
ePWM/HRPWM Re-map Register
DESCRIPTION
3.6.1
OSC and PLL Block
shows the OSC and PLL block.
OSCCLK
OSCCLK
0
PLLSTS[OSCOFF]
PLL
VCOCLK
n
n
≠
0
OSCCLK or
VCOCLK
/1
/2
/4
CLKIN
To
CPU
XCLKIN
(3.3-V clock input
from external
oscillator)
PLLSTS[PLLOFF]
External
Crystal or
Resonator
X1
On-chip
oscillator
X2
PLLSTS[DIVSEL]
4-bit Multiplier PLLCR[DIV]
Figure 3-9. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the 2833x/2823x devices using
the X1 and X2 pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of
the following configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low . The logic-high level in this case should not exceed V
DDIO
.
2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2
pin should be left unconnected and the XCLKIN pin tied low . The logic-high level in this case should
not exceed .
Copyright © 2007–2011, Texas Instruments Incorporated
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